Design Verification Club
Event
- Title:
- Bangalore - Q2 2009 - Sunil Kumar and Narasimha Karunakar
- When:
- 05.22.2009 10.30 h - 13.00 h
- Where:
- Taj Residency Hotel on M.G. Rd, Vijayanagar 2 hall - Bangalore
- Category:
- Bangalore
Description
Mixed Signal Validation and Low-Power Verification
Speakers:
Narasimha Karunakar, AMD Bangalore
Low Power Verification Challenges - pdf
- Narasimha Karunakar is currently working as a Senior Design Engineer at AMD Bangalore and responsible for setting up the flow and driving the methodology for Power Aware Simulations for complicated Microprocessors.
- Narasimha has been working in ASIC design and verification since 2000.
- His expertise is mainly in the areas of functional verification by using state of the art verification techniques using Specman and VERA for complex ASICs. Narasimha was involved in development of complex test benches & verification of modules in Network chips and storage devices.
- Narasimha has also worked on Design, Synthesis, and Timing Analysis as part of ASIC Design flows. Narasimha has won several “Best Performer” awards for his outstanding and consistent performance.
Sunil Kumar, Intel Bangalore
Trends in Mixed Signal Validation - pdf
- Sunil Kumar is leading Mixed Signal Validation (MSV) of next generation microprocessor at Intel, Bangalore.
- Sunil has been involved in defining MSV methodology in multiple projects.
- Before MSV, he contributed in design and validation of 10Gb Ethernet Switch ASIC.
- Sunil started his career in 1996 from C-DOT where he was involved in the design of two generations of ATM Switching systems. Sunil has BE from MNNIT, Allahabad and MSc (Engg.) from IISc, Bangalore.
Agenda:
| 10:30-11am | Coffee/Snacks |
| 10:45-11:00am | Welcome the gathering followed by first Speaker introduction – Dixit Betaraya |
| 11-11:30am | Trends in Mixed Signal Validation” by Sunil Kumar B, Intel, Bangalore |
| 11:30-11:35am | Speaker introduction – Nitin Makhija |
| 11:35-12:05pm | Challenges, possible solutions and flow changes for low power design verification of complex chips by Narasimha Karunakar, AMD, Bangalore |
| 12:15-1pm | Lunch/interaction |
Registration:
DVClub membership is free and is open to all non-service provider semiconductor professionals. Most members work in verification, but there are also plenty of entrepreneurs, professors, students, managers, investors, and even design engineers who attend. Participation by service providers (solicitors) is limited to event sponsors, who supply the funds for DVClub events.
Help us plan for a proper setup and RSVP here.
Venue
- Venue:
- Taj Residency Hotel on M.G. Rd, Vijayanagar 2 hall - Website
- Street:
- 41/3, Mahatma Gandhi Road,
- ZIP:
- 560 001
- City:
- Bangalore
- Country:
-
Description
No description
EventList powered by schlu.net