Help us Plan for a Proper Setup and RSVP for this Free Event.

Headlining Speaker:

Brian Bailey – Verification Guru

Topic:

Is it time to declare a verification war?

It is often said that verification is an art, but that has led us to statistics that show that success rates for chips are low. Perhaps it is time to think of it as war. In the words on Sun Tzu “If you know the enemy and know yourself, your victory will not stand in doubt”. In this talk I will examine some of the fundamentals of verification and coverage and look at how far we may have strayed from the necessary understanding to win. In addition, some modern verification tools may be compounding those problems. Recent developments in the area of objective coverage measurement will be discussed along with the results of what may be a hot discussion at the Haifa Verification Conference this year.

Bio:

• Brian currently stays busy as a reviewer, technical program member and track chair for a number of conferences, including DATE and DAC as well as serving on the Technical Advisory Board for Jasper Design Automation.
• Brian currently serves as chair of the Accellera Interfaces Technical Committee, which has successfully developed a co-emulation standard that is now getting widespread adoption in the market.
• In 2007, Brian published, along with Grant Martin and Andrew Piziali, what is becoming the definitive work on the Electronic System Level (ESL) Design and Verification space.
• He has also authored two books:
  The functional verification of digital systems, and
  Taxonomy for the development and verification of electronic systems

• Brian's work has resulted in four patents issued with others currently pending.
• Brian's diverse background has also given him considerable experience in the areas of:

• reference flows
• hardware/software co-verification
• multi-level, mixed signal simulation
• creating debug tools
• development of waveform languages
• graphical front end tools
• hardware accelerators

• As a point of note, Brian also worked as engineering and project manager on HILO, the worlds first commercial RTL simulator at Brunel University in London – 1987.

DVClub University Speakers

DVClub University Speakers

Mike Stellfox - Technical Lead of Verification Solutions Architecture Team, Cadence

• Topic: Metrics Driven Verification

Doug Smith -  Senior Technical Engineering Consultant, Doulos

• Topic: Using bind for Class-based Testbench Reuse with Mixed-Language Designs
  
  SystemVerilog offers a simple way to reuse any block-level testbench without modifications in a system environment, which also work with mixed-language designs.  Using the SystemVerilog bind command and a few simple guidelines, reuse of block-level testbenches could not be simpler.  This presentation sets forth a simple methodology compatible with any class-based testbench that enables effortless and maximum reuse of block-level verification environments. 

Mark Gillman - Senior DV Engineer,  Denali

• Topic: OVM

Luis Morales - Certess

• Topic: Verification Coverage Tools
  
  “If there were a bug in your design, could the verification environment find it?”  Functional qualification is the first technology to provide an objective answer to this fundamental question. It is an important addition to the solutions available for the increasingly challenging task of delivering functionally correct silicon on time and on budget.

Agenda