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Adam Krolnik
- Dallas - Q4 2005 - Adam Krolnik
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The Design is not Correct! - pdf
- Adam is the verification manager of ZSP (DSP) Technology of LSI Logic
Corp in Plano Texas. His career as a verification engineer spans 15
years involving verification of microprocessors, memory systems, cache
coherency systems, processor buses, and bus bridges. He has also been
involved in creating custom assertion tools. He has been involved in
the IEEE verilog standards group, and the Accellera SystemVerilog
standards group. He is the co-author of "Assertion-Based Design", a
book on efficient use of assertions during the design process. He holds
a BSEE degree from the University of Wisconsin in Madison.
Kelly Larson - Analog Devices (ADI)
- Austin - Q3 2005 - Kelly Larson, Mike Pedneau
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Using PSL Assertions at Analog Devices - pdf
- Kelly
Larson has 15 years experience in the verification of complex
microprocessors, DSPs, and SoC. Prior to joining ADI he worked for HP
as part of the PA Risc development team. Kelly currently works in ADI's
Austin location where he manages the verification leads, develops
verification strategies, and establishes roadmaps for new
methodologies.
The full version of this presentation is available as a Webinar: Using PSL Assertions for Functional Coverage
Mark McDermott
- Austin - Q4 2005 - Mark McDermott
- Mark
McDermott has 28 years of experience in the management and product
development of silicon systems. Mark is also a serial entrepreneur,
having co-founded six companies during his career. He has led
engineering teams in the development of PowerPC processors and Intel
x86 processors and has 19 patents in the area of microprocessor design
and test. (bio - pdf)
Jon Michelson
- Silicon Valley - Q4 2005 - Jon Michelson
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The Future of SystemVerilog Verification - pdf
- Jon Michelson has over nine years of experience verifying complex
designs and writing verification infrastructure tools. He received his
bachelor’s and masters’s degree in electrical engineering and computer
science from M.I.T. He is a co-author of "The Art of Verification with
SystemVerilog Assertions" and "The Art of Verification with VERA." He
was a co-designer of a verification language and methodology at Silicon
Graphics. Michelson is currently at Cisco Systems, designing and
verifying complex systems."
Jon's new book "The Art of Verification with SystemVerilog Assertions" can be preordered at the DV Central web site.
Mike Pedneau - Texas Instruments
- Austin - Q3 2005 - Kelly Larson, Mike Pedneau
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DV Employment Future - pdf
- Mike Pedneau is DSP Verification Manager for TI's Austin location. His
career in verification spans 18 years, including time served at AMD,
Ross, and as a verification mercenary.
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