Tags
analog automation analog verification Architecture ASIC Brian Bailey Cadence checkers C model Complex Architectures corner cases coverage coverage driven methodology coverage grid Coverage metrics coverage monitors DAC Dave Whipp Debugging Design design entry designers' guide consulting digital verification directed assembly code tests directed testing Distribution of Coverage Points Doug Smith Doulos DVClub DVCon emulation Eric Hennenhoefer ESL formal verification functional design verification functional verification general purpose microprocessor modeling OVM RTL testbench SystemVerilog Technical Review UVM Validation Verification verification jobs
Tag Archives: Verification
Posted on December 8, 2010 by saturday
Doug Smith of Doulos announced today topic selections for his upcoming verification tutorials at DVClub Austin on December 15th. This promises to be our biggest event of the year. If you’re not already registered to attend, then we invite you … Continue reading →
Posted in Austin, Design Verification
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Tagged Doug Smith, Doulos, modeling, OVM, SystemVerilog, UVM, Verification
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Posted on October 19, 2010 by saturday
On November 8th, Michael Theobold of D.E. Shaw Research will present at DVClub Silicon Valley on Anton - a special purpose supercomputer. It was named after Anton van Leeuwenhoek, the father of microbiology, and was designed expressly for simulating protein … Continue reading →
Posted in Design Verification, Silicon Valley
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Tagged Architecture, ASIC, Complex Architectures, D.E. Shaw Research, modeling, Supercomputer, Verification
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Posted on May 20, 2010 by saturday
By Hemendra Talesara Complexity In his recent presentation discussing verification of the Power7 processor, John Ludden of IBM opened with a quote from an IBM exec more than a decade ago. “it’s not rocket science”- a perception held by some … Continue reading →
Posted in Austin, Design Verification, Technical Review
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Tagged Architecture, checkers, Complex Architectures, functional design verification, functional verification, RTL testbench, Technical Review, Verification
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Posted on February 11, 2010 by admin
By Richard Goering on February 1, 2010. This article is reposted from the Cadence blog. Can verification engineers gain control over the verification process, and stop being full-time firefighters? With proper planning, communication, and organization, the answer is “yes,” according … Continue reading →
Posted in Boston, Silicon Valley, Technical Review
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Tagged Allison Goodman, Validation, Verification
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Posted on August 5, 2009 by admin
Written by Brian Bailey for DVClub At DAC this year, one of the main themes was ESL but not in the usual sense of it having a lot of promise but little to deliver. This year it had a lot … Continue reading →
Posted in DV Conferences
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Tagged Brian Bailey, coverage, DAC, Debugging, Design, ESL, modeling, Technical Review, Verification, virtual platforms
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Posted on June 10, 2009 by admin
Preliminary Call for Papers: 10th International Workshop on Microprocessor Test and Verification (MTV 2009) December 7-8, 2009, Hyatt Regency On Town Lake, Austin, Texas, USA. Website: http://mtv.ece.ucsb.edu/MTV/ This is the 10th edition of the MTV Workshop, a testament to its … Continue reading →
Posted in Austin, DV Conferences
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Tagged coverage, Debugging, emulation, formal verification, functional verification, microprocessor, modeling, multimedia processor, performance testing, SoC, test, Validation, Verification
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Posted on October 2, 2008 by eric
Eric reviews John Ludden’s verification strategy for IBM’s POWER6 architecture and discusses the complexity of verifying a modern in-order processor. Continue reading →
Posted in Technical Review
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Tagged High Frequency, IBM, In Order, infinite state, John Ludden, MP/SMT, MT, Out of Order, POWER5, POWER6, RAS, Simultaneous Multi Threading, SMT, Software Simulation, Verification
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Posted on August 28, 2008 by admin
This blog explores the theories of NVIDIA’s Dave Whipp on restructuring DV workflow by using C models in place of the natural language specification. Continue reading →
Posted in Technical Review
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Tagged Architecture, ASIC, C model, checkers, Dave Whipp, Debugging, Design, ESL, Methodology, NVIDIA, Spec, testbench, Validation, Verification
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