Conferences aren’t my favorite events to attend. They tend to be dominated by the big three EDA companies, and the messages are usually just a variation on what was said last year. However, there is always something useful to glean if you listen hard enough, and I think DVCon this year is no exception.

While DVCon is generally more of a verification conference, I found design related topics surprisingly absent. Cliff Cummings presented a good paper on using SystemVerilog’s unique, priority, and 1800-2009’s unique0 constructs, but other than that, everything centered on verification except for some brief discussion on C synthesis at a panel and the SystemC synthesizable subset at the OSCI tutorial session. Verification continues to dominate the industry’s focus as well as high-level modeling.

In fact, I felt that the major topics at DVCon this year were verification methodologies (VMM & OVM), TLM 2.0, and SystemVerilog. I’ll just say a brief word on each.

Both VMM and OVM have recently been updated. Synopsys has added significant features to VMM in their 1.2 release. Doulos sponsored a VMM 1.2 tutorial along with other VMM Central partners highlighting the new features like TLM 2.0 support, implicit phasing, and enhanced testbench structure and configuration as well as explaining how to exploit the RAL register package. In conjunction, Doulos gave away their new VMM 1.2 Golden Reference Guide and has made available a VMM 1.2 tutorial on their website. OVM is also recently updated (version 2.1), but it hasn’t majorly changed so the story is still much the same.

The SystemC NASCUG meeting was co-located with DVCon and there seemed to be a lot of interest around TLM 2.0. OSCI also hosted a TLM 2.0 tutorial session and there was a user paper session centering on TLM. VMM’s TLM 2.0 implementation generated a bit of interest as well. While I don’t use TLM for SystemC modeling, given all the buzz about it I have to conclude that it’s being well-embraced by the industry and it looks like it’s here to stay. I certainly find TLM connections quite useful in an OVM/VMM testbench.

Personally, I found the most interesting papers were those discussing SystemVerilog. Dave Rich from Mentor proposed a multiple class inheritance enhancement, which seems to have great potential. Cliff Cummings talked about enhancing the language to handle X optimism and pessimism. Eduard Cerny discussed new SV-2009 checker and assertion features. But I have to admit, the nagging question I have is, “Will this language everstop exploding?” If I may say, SystemVerilog is like an ever-expanding patchwork, where piece after piece is added but none of it ever seems to truly fit together. And every year, more and more ideas are proposed to enhance it. Oh well, I guess it’s what we have to live with. For those not converted yet to SystemVerilog, my colleague, Alan Fitch, wrote in his DVCon paper, “How to Achieve Sample-Based Coverage Using VHDL” — quite a unique topic among all the other presented papers. Keep an eye out on the Doulos website for the upload of his paper if you’re interested. I usually write papers that show how to work with or around what we already have. That’s why I presented a paper on matching asynchronous behaviors using SystemVerilog assertions (soon to be uploaded to the Doulos website), and likewise, my colleague, John Aynsley, presented a great paper on using the DPI to interface with C/C++ models.

I think the most exciting news at DVCon this year came from Accellera. Accellera’s Verification IP (VIP) technical subcommittee has announced that a universal verification methodology (UVM) is planned for release mid-March. UVM will be based on OVM 2.0.3 and have features of VMM incorporated into it. The amazing thing is that Synopsys, Cadence, and Mentor are all unanimously behind UVM. I think this will definitely reshape the verification methodology story in the industry over the coming year. I was also pleased to hear that the unified coverage interoperability standard (UCIS) is due out in October. This should give us a common way to access and merge all of our coverage data. Lastly, I was rather surprised by the take-away message from Brian Bailey’s panel on minimizing verification time and effort—engineers need more training!! As a trainer, I couldn’t agree more!

Doug Smith

Written by Brian Bailey for DVClub

At DAC this year, one of the main themes was ESL but not in the usual sense of it having a lot of promise but little to deliver. This year it had a lot to say in two main categories, the first being high-level synthesis and the second being virtual platforms. Given the main focus of the DVClub, I will only talk about the virtual platforms. Quite a few companies were showing their platforms, including Mentor, Synopsys, CoFluent, CoWare and I am sure there were others. These platforms are at two main levels of abstraction.

At the higher end are platforms typified by the Synopsys Innovator which are primarily intended for software development, verification and debug. These are loosely timed platforms where speed is one of the primary factors. Then there are the more accurately timed platforms such as the Mentor Vista product which is intended for architectural exploration of the hardware system. Other companies such as Imperas also provide high performance processor models that fit into these platforms. The one thing common to most of them, and the main reason why they were such a force at DAC this year was the introduction of the OSCI TLM 2.0 specification at last years DAC. These platforms can now exchange models (although there are still some minor issues) and that is huge. A lack of models was perhaps the biggest reason why these platforms have not taken off. That roadblock has now essentially been removed.

Some new companies such as Docea were touting high-level power estimation platforms, and just for completeness, Mentor, Cadence, AutoESL, BlueSpec, Synfora, Forte and I am sure others were showing high level synthesis tools.

There was a panel session on Tuesday about virtual platforms that was one of the worst DAC panels I have ever sat through. It was supposed to address the issue of if platforms should be virtual, physical or hybrid. Ron Wilson tried hard to make it sound fun and interesting, but this is not a debate topic – we all want models in any form that we can get them in and we want them to play together nicely! End of debate – end of panel – nothing to discuss, just some solid engineering that has to happen.

On Wednesday, there was a much better conceived workshop on virtual platforms that I had been asked to speak at. The workshop was organized by Soha Hassoun and Larry Lapidas and included lots of interesting talks about platforms at many levels of abstraction and intended for many uses. Over lunch was a panel session that also had some much more interesting discussions. Sadly, I had to leave in order moderate a panel entitled “The Holy Grail of Verification – Coverage Closure”. Any of you who have listened to my DVClub talks will know that I have strong views on that issue, but unfortunately I was moderating so had to keep my mouth shut. Ouch that was difficult!

TLM 2.0 was finally ratified at DAC this year – I wonder if that will have a similar impact on next years DAC. I am hoping to see many more platforms which are extensible – add timing as a layer, add power as a layer, add X as a layer. Then we will have something that will play through multiple levels of abstraction and start to tie together the whole ESL flow.

Brian Bailey – keeping you covered
brian_bailey at acm.org

10th International Workshop on Microprocessor Test and Verification (MTV 2009)
December 7-8, 2009, Hyatt Regency On Town Lake, Austin, Texas, USA.

Website: http://mtv.ece.ucsb.edu/MTV/

This is the 10th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross- examination of test and verification experiences and innovative solutions. MTV has been held in Austin for the last 8 years, so please plan on participating in order to make this another successful forum.

Purpose

The purpose of this workshop is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa.

Topics

AREAS OF INTEREST include, but not limited to:

• Validation of microprocessors and SOCs
• Test/Verification of multimedia processors
• Performance testing
• High-level test generation for functional verification
• Emulation techniques
• Silicon debugging
• Formal techniques and their applications
• Verification coverage
• Test Generation at the transistor level
• Equivalence checking of custom circuits
• ESL Methodology
• Virtual Platforms
• Software verification
• Circuit level verification
• Switch-level circuit modeling
• Timing validation techniques
• Path analysis for verification or test
• Design error models
• Design error diagnosis
• Design for Testability or Verifiability
• Optimizing SAT procedures with applications to testing and formal verification

Important dates

Submission: Sept 1, 2009
Notification: Oct 1, 2009
Final version due: Nov 1, 2009