Tags
analog automation analog verification Architecture ASIC Brian Bailey Cadence checkers C model Complex Architectures corner cases coverage coverage driven methodology coverage grid Coverage metrics coverage monitors DAC Dave Whipp Debugging Design design entry designers' guide consulting digital verification directed assembly code tests directed testing Distribution of Coverage Points Doug Smith Doulos DVClub DVCon emulation Eric Hennenhoefer ESL formal verification functional design verification functional verification general purpose microprocessor modeling OVM RTL testbench SystemVerilog Technical Review UVM Validation Verification verification jobs
Tag Archives: modeling
Posted on December 8, 2010 by saturday
Doug Smith of Doulos announced today topic selections for his upcoming verification tutorials at DVClub Austin on December 15th. This promises to be our biggest event of the year. If you’re not already registered to attend, then we invite you … Continue reading →
Posted in Austin, Design Verification
|
Tagged Doug Smith, Doulos, modeling, OVM, SystemVerilog, UVM, Verification
|
Comments Off
Posted on October 19, 2010 by saturday
On November 8th, Michael Theobold of D.E. Shaw Research will present at DVClub Silicon Valley on Anton - a special purpose supercomputer. It was named after Anton van Leeuwenhoek, the father of microbiology, and was designed expressly for simulating protein … Continue reading →
Posted in Design Verification, Silicon Valley
|
Tagged Architecture, ASIC, Complex Architectures, D.E. Shaw Research, modeling, Supercomputer, Verification
|
Comments Off
Posted on March 5, 2010 by admin
By Doug Smith of Doulos Conferences aren’t my favorite events to attend. They tend to be dominated by the big three EDA companies, and the messages are usually just a variation on what was said last year. However, there is … Continue reading →
Posted in DV Conferences, Technical Review
|
Tagged Brian Bailey, Cadence, Design, Doug Smith, Doulos, DVCon, Mentor, modeling, OVM, Synopsys, SystemC, SystemVerilog, UVM, VMM
|
1 Comment
Posted on August 5, 2009 by admin
Written by Brian Bailey for DVClub At DAC this year, one of the main themes was ESL but not in the usual sense of it having a lot of promise but little to deliver. This year it had a lot … Continue reading →
Posted in DV Conferences
|
Tagged Brian Bailey, coverage, DAC, Debugging, Design, ESL, modeling, Technical Review, Verification, virtual platforms
|
1 Comment
Posted on June 10, 2009 by admin
Preliminary Call for Papers: 10th International Workshop on Microprocessor Test and Verification (MTV 2009) December 7-8, 2009, Hyatt Regency On Town Lake, Austin, Texas, USA. Website: http://mtv.ece.ucsb.edu/MTV/ This is the 10th edition of the MTV Workshop, a testament to its … Continue reading →
Posted in Austin, DV Conferences
|
Tagged coverage, Debugging, emulation, formal verification, functional verification, microprocessor, modeling, multimedia processor, performance testing, SoC, test, Validation, Verification
|
Comments Off
