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analog automation analog verification Architecture ASIC Brian Bailey Cadence checkers C model Complex Architectures corner cases coverage coverage driven methodology coverage grid Coverage metrics coverage monitors DAC Dave Whipp Debugging Design design entry designers' guide consulting digital verification directed assembly code tests directed testing Distribution of Coverage Points Doug Smith Doulos DVClub DVCon emulation Eric Hennenhoefer ESL formal verification functional design verification functional verification general purpose microprocessor modeling OVM RTL testbench SystemVerilog Technical Review UVM Validation Verification verification jobs
Tag Archives: Mentor
Posted on March 5, 2010 by admin
By Doug Smith of Doulos Conferences aren’t my favorite events to attend. They tend to be dominated by the big three EDA companies, and the messages are usually just a variation on what was said last year. However, there is … Continue reading →
Posted in DV Conferences, Technical Review
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Tagged Brian Bailey, Cadence, Design, Doug Smith, Doulos, DVCon, Mentor, modeling, OVM, Synopsys, SystemC, SystemVerilog, UVM, VMM
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