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analog automation analog verification Architecture ASIC Brian Bailey Cadence checkers C model Complex Architectures corner cases coverage coverage driven methodology coverage grid Coverage metrics coverage monitors DAC Dave Whipp Debugging Design design entry designers' guide consulting digital verification directed assembly code tests directed testing Distribution of Coverage Points Doug Smith Doulos DVClub DVCon emulation Eric Hennenhoefer ESL formal verification functional design verification functional verification general purpose microprocessor modeling OVM RTL testbench SystemVerilog Technical Review UVM Validation Verification verification jobs
Tag Archives: Is it time to declare a verification war?
Posted on March 23, 2009 by admin
By Grant Martin This blog post originally appeared at: http://www.chipdesignmag.com/martins/2009/03/19/bailey-on-verification-at-the-club/ — March 19, 2009 @ 11:14 pm Today I attended the latest meeting of the Silicon Valley branch of the DVClub. For those not familiar with the DVClub (DV = … Continue reading →
Posted in Silicon Valley, Technical Review
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Tagged Brian Bailey, DVClub, Eric Hennenhoefer, Is it time to declare a verification war?, Silicon Valley, Technical Review
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