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analog automation analog verification Architecture ASIC Brian Bailey Cadence checkers C model Complex Architectures corner cases coverage coverage driven methodology coverage grid Coverage metrics coverage monitors DAC Dave Whipp Debugging Design design entry designers' guide consulting digital verification directed assembly code tests directed testing Distribution of Coverage Points Doug Smith Doulos DVClub DVCon emulation Eric Hennenhoefer ESL formal verification functional design verification functional verification general purpose microprocessor modeling OVM RTL testbench SystemVerilog Technical Review UVM Validation Verification verification jobs
Tag Archives: functional verification
Posted on May 20, 2010 by saturday
By Hemendra Talesara Complexity In his recent presentation discussing verification of the Power7 processor, John Ludden of IBM opened with a quote from an IBM exec more than a decade ago. “it’s not rocket science”- a perception held by some … Continue reading →
Posted in Austin, Design Verification, Technical Review
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Tagged Architecture, checkers, Complex Architectures, functional design verification, functional verification, RTL testbench, Technical Review, Verification
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Posted on June 10, 2009 by admin
Preliminary Call for Papers: 10th International Workshop on Microprocessor Test and Verification (MTV 2009) December 7-8, 2009, Hyatt Regency On Town Lake, Austin, Texas, USA. Website: http://mtv.ece.ucsb.edu/MTV/ This is the 10th edition of the MTV Workshop, a testament to its … Continue reading →
Posted in Austin, DV Conferences
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Tagged coverage, Debugging, emulation, formal verification, functional verification, microprocessor, modeling, multimedia processor, performance testing, SoC, test, Validation, Verification
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