Posts Tagged ‘DAC’

DAC 2009 in Review

Wednesday, August 5th, 2009 by admin

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Written by Brian Bailey for DVClub

At DAC this year, one of the main themes was ESL but not in the usual sense of it having a lot of promise but little to deliver. This year it had a lot to say in two main categories, the first being high-level synthesis and the second being virtual platforms. Given the main focus of the DVClub, I will only talk about the virtual platforms. Quite a few companies were showing their platforms, including Mentor, Synopsys, CoFluent, CoWare and I am sure there were others. These platforms are at two main levels of abstraction.

At the higher end are platforms typified by the Synopsys Innovator which are primarily intended for software development, verification and debug. These are loosely timed platforms where speed is one of the primary factors. Then there are the more accurately timed platforms such as the Mentor Vista product which is intended for architectural exploration of the hardware system. Other companies such as Imperas also provide high performance processor models that fit into these platforms. The one thing common to most of them, and the main reason why they were such a force at DAC this year was the introduction of the OSCI TLM 2.0 specification at last years DAC. These platforms can now exchange models (although there are still some minor issues) and that is huge. A lack of models was perhaps the biggest reason why these platforms have not taken off. That roadblock has now essentially been removed.

Some new companies such as Docea were touting high-level power estimation platforms, and just for completeness, Mentor, Cadence, AutoESL, BlueSpec, Synfora, Forte and I am sure others were showing high level synthesis tools.

There was a panel session on Tuesday about virtual platforms that was one of the worst DAC panels I have ever sat through. It was supposed to address the issue of if platforms should be virtual, physical or hybrid. Ron Wilson tried hard to make it sound fun and interesting, but this is not a debate topic – we all want models in any form that we can get them in and we want them to play together nicely! End of debate – end of panel – nothing to discuss, just some solid engineering that has to happen.

On Wednesday, there was a much better conceived workshop on virtual platforms that I had been asked to speak at. The workshop was organized by Soha Hassoun and Larry Lapidas and included lots of interesting talks about platforms at many levels of abstraction and intended for many uses. Over lunch was a panel session that also had some much more interesting discussions. Sadly, I had to leave in order moderate a panel entitled “The Holy Grail of Verification – Coverage Closure”. Any of you who have listened to my DVClub talks will know that I have strong views on that issue, but unfortunately I was moderating so had to keep my mouth shut. Ouch that was difficult!

TLM 2.0 was finally ratified at DAC this year – I wonder if that will have a similar impact on next years DAC. I am hoping to see many more platforms which are extensible – add timing as a layer, add power as a layer, add X as a layer. Then we will have something that will play through multiple levels of abstraction and start to tie together the whole ESL flow.

Brian Bailey – keeping you covered
brian_bailey at acm.org