Conferences aren’t my favorite events to attend. They tend to be dominated by the big three EDA companies, and the messages are usually just a variation on what was said last year. However, there is always something useful to glean if you listen hard enough, and I think DVCon this year is no exception.

While DVCon is generally more of a verification conference, I found design related topics surprisingly absent. Cliff Cummings presented a good paper on using SystemVerilog’s unique, priority, and 1800-2009′s unique0 constructs, but other than that, everything centered on verification except for some brief discussion on C synthesis at a panel and the SystemC synthesizable subset at the OSCI tutorial session. Verification continues to dominate the industry’s focus as well as high-level modeling.

In fact, I felt that the major topics at DVCon this year were verification methodologies (VMM & OVM), TLM 2.0, and SystemVerilog. I’ll just say a brief word on each.

Both VMM and OVM have recently been updated. Synopsys has added significant features to VMM in their 1.2 release. Doulos sponsored a VMM 1.2 tutorial along with other VMM Central partners highlighting the new features like TLM 2.0 support, implicit phasing, and enhanced testbench structure and configuration as well as explaining how to exploit the RAL register package. In conjunction, Doulos gave away their new VMM 1.2 Golden Reference Guide and has made available a VMM 1.2 tutorial on their website. OVM is also recently updated (version 2.1), but it hasn’t majorly changed so the story is still much the same.

The SystemC NASCUG meeting was co-located with DVCon and there seemed to be a lot of interest around TLM 2.0. OSCI also hosted a TLM 2.0 tutorial session and there was a user paper session centering on TLM. VMM’s TLM 2.0 implementation generated a bit of interest as well. While I don’t use TLM for SystemC modeling, given all the buzz about it I have to conclude that it’s being well-embraced by the industry and it looks like it’s here to stay. I certainly find TLM connections quite useful in an OVM/VMM testbench.

Personally, I found the most interesting papers were those discussing SystemVerilog. Dave Rich from Mentor proposed a multiple class inheritance enhancement, which seems to have great potential. Cliff Cummings talked about enhancing the language to handle X optimism and pessimism. Eduard Cerny discussed new SV-2009 checker and assertion features. But I have to admit, the nagging question I have is, “Will this language everstop exploding?” If I may say, SystemVerilog is like an ever-expanding patchwork, where piece after piece is added but none of it ever seems to truly fit together. And every year, more and more ideas are proposed to enhance it. Oh well, I guess it’s what we have to live with. For those not converted yet to SystemVerilog, my colleague, Alan Fitch, wrote in his DVCon paper, “How to Achieve Sample-Based Coverage Using VHDL” — quite a unique topic among all the other presented papers. Keep an eye out on the Doulos website for the upload of his paper if you’re interested. I usually write papers that show how to work with or around what we already have. That’s why I presented a paper on matching asynchronous behaviors using SystemVerilog assertions (soon to be uploaded to the Doulos website), and likewise, my colleague, John Aynsley, presented a great paper on using the DPI to interface with C/C++ models.

I think the most exciting news at DVCon this year came from Accellera. Accellera’s Verification IP (VIP) technical subcommittee has announced that a universal verification methodology (UVM) is planned for release mid-March. UVM will be based on OVM 2.0.3 and have features of VMM incorporated into it. The amazing thing is that Synopsys, Cadence, and Mentor are all unanimously behind UVM. I think this will definitely reshape the verification methodology story in the industry over the coming year. I was also pleased to hear that the unified coverage interoperability standard (UCIS) is due out in October. This should give us a common way to access and merge all of our coverage data. Lastly, I was rather surprised by the take-away message from Brian Bailey’s panel on minimizing verification time and effort—engineers need more training!! As a trainer, I couldn’t agree more!

Doug Smith

Last week I had the pleasure of attending a DV Club lunch presentation from Dr. Henry Chang of Designers’ Guide Consulting on “What the Digital Verification Engineer Needs to Know about Analog Verification”.

The talk was very engaging, where Dr. Chang’s comments on the relatively primitive state of analog verification confirmed my observations in talking with customers and Trailblazer partners. Specifically:

1 – In the eyes of digital verification people, analog verification looks like digital verification circa 1990. This isn’t meant as a criticism of analog developers — Dr. Chang reviewed the many reasons why this gap exists, and why they will likely persist for years into the future. For example, in order to effectively support the hierarchical circuit construction methodologies commonly used in the digital world, depending on the type circuit you are simulating analog simulators would have to become literally 1,000,000 times faster than they are today.

2 – Dr. Chang noted that very trivial, functional A-D interface errors are depressingly common in mixed signal designs. Even worse: such bugs are typically catastrophic (i.e. the chip is dead-on-arrival from the fab)

3 – The level of automation vs. the digital world is very low. Despite the growing complexity of pure analog blocks, most design entry is still done with schematic capture and not high-level design languages (although this is slowly changing). Debug? It’s all about eyeballing golden waveforms.

There was much more to the talk, but these three highlights stood out in my mind because myself and my fellow Trailblazers have also seen 1, 2, and 3 in our customer base. As such, I was “relieved” (in an ironic, negative sense) to hear that an expert like Dr. Chang is seeing the same things too. Do you out there in the blogsphere see all this too? Have you seen any analog users overcome 1, 2, or 3?

In a vaguely related note:
Driving back to my office from the talk, I was also struck by an analogy to the hardware/software co-verification space, where verification in this mixed domain is also relatively primitive compared to pure digital RTL verification. My colleague Jason Andrews captures this issue nicely in his recent post “Is anybody out there a Software Verification Engineer?”

In conclusion, I’d argue that at the 50,000ft level, issues 1 and 2 are factors in both the AMS and HW/SW domains (and for issue 3, you have to admit there is a lot of “bad” automation in the HW/SW domain; but that’s the subject of another blog post). The silver lining in these clouds is that the hunger for automated, metric-driven solutions in the AMS space is growing, and thus the EDA business has some future opportunities here whatever doldrums the economy might be in today.

P.S. If you haven’t been to one of these “DV Club” events, you are really missing out. The format is typically an in depth talk on some design or verification topic given over lunch, and the speakers have always been very informative. These events also draw a good sized audience (I’ve never seen less than 50 people at the Silicon Valley area events I go to), so the networking is great. Note that in addition to Silicon Valley, they hold these “lunch & learns” in Austin, Bangalore, Boston, Bristol UK, Dallas, RTP, and San Diego. Here is the DV Club events calendar for more info:
http://www.dvclub.org