We thought that it might make for interesting reading to compile a list of the most downloaded presentations from past DVClub events.

For those of you unfamiliar with DVClub, membership is free and is open to all non-service provider semiconductor professionals. Most members work in verification, but there are also plenty of entrepreneurs, professors, students, managers, investors, and even design engineers who attend. If you’re interested and would like to learn more, why not join the club?

Chuck Alley, IBM

Using PSL and FoCs for Functional Coverage Verification

Bob Colwell, Intel (Retired)

The Validation Attitude

Raj Dayal, Qualcomm

Managing Deployment of SVAs in Your Project

Ish Kumar Dham, Texas Instruments

Design Verification to Application Validation of a Multiprocessor SoC

Sanjay Gupta, IBM

Cell Verification Metrics

Narasimha Karunakar, AMD

Low-Power Verification Challenges

Mark A Firstenberg, IBM

Experience with Formal Methods, Especially Sequential Equivalence Checking

Jai Kumar, Sun

Leveraging Low-Cost FPGA Prototyping for Validation of Highly Threaded Server-on-Chip

John Ludden, IBM

Mainline Functional Verification of IBM’s POWER7 Processor Core

Milind Padhye, Freescale

Wireless Low Power and Verification Challenges

Somdipta Basu Roy, Texas Instruments

OMAP Verification

Scott Runner, Qualcomm

Verification of Wireless SoCs: No Longer in the Dark Ages

Sakar Jain, Freescale

Verification of the QorIQ Communication Platform’s CoreNet Fabric with SystemVerilog

Shahram Salamian, Intel

Intel Atom Processor Pre-Silicon Verification Experience

CPU Verification Metrics

Jason Stinson, Intel

Pre-Si Verification for Post-Si Validation

Paul Tobin, AMD

Verification in a Global Design Community

Durgam Vahia, Sun

Mapping Server-Class Multi-Threaded OpenSPARC T1 Processor Core on FPGAs

David Williamson, ARM

Verification Metrics

Paul Zehr, Intel

Intel Xeon Pre-Silicon Validation

Posted in Technical Review | 2 Comments

By Hemendra Talesara

Complexity

In his recent presentation discussing verification of the Power7 processor, John Ludden of IBM opened with a quote from an IBM exec more than a decade ago. “it’s not rocket science”- a perception held by some members of the management and design communities at that time.

However, designs have become a whole lot more complex over time. The Power7 processor at 45nm has 1.2B transistors on a 567 sq. mm die, supporting 8 cores with 4 threads each, an on-chip eDRAM, 3 levels of caches and 2 DDR memory controllers. Yet as verification complexity multiplies in this multi-threaded design, it’s very helpful to have some of the more advanced tools and methodology at your disposal.

Tools and Methodology

Fortunately for Ludden and the Power7 team, IBM has invested in verification technology for years (in spite the quote from the exec). The company continues to develop and rely on in-house tools for many of the advanced verification technologies for processor-specific testing. These include the test-bench, multi-thread test generators, hardware accelerators, formal and semi-formal tools, micro-architecture checkers (API based), cache coherency checkers and coverage tools. Exercisers
originally developed for post-silicon validation were used to exploit the hardware acceleration platform. Forty-five thousand coverage points were organized to assist with big picture and were used to re-direct the test generator and exercisers for accelerators.

To support corner case testing for events that occur rarely, especially in multi-threaded scenarios, software irritator threads were used. These irritators are capable of creating the worst possible contentions. Through their application, twenty-three high quality bugs were revealed hiding in the corners.

A methodical application of these tools and technology clearly captured and advanced the industry best practices.

Designing for Verification

Designing for Verification was an important element in managing the overall risk to verification time line. IBM minimized the risks by maintaining a tight interaction between the specification and verification teams during the design phase and allowing the verification team to maintain architectural changes. “Chicken switches” were placed in silicon that allowed verification team to back-off an area considered risky or possible of otherwise compromising the verification effort. These switches provide workarounds, with some small impact on performance but no functional change, for accessing difficult to verify micro architectural features. Hardware irritators were also used to enable stress testing of corner cases in both pre-silicon and post-silicon testing.

Conclusion

The Power7 draws many architectural features from the Power5 and 6 designs, although it is a much more complex and powerful processor with a much shorter verification cycle. Ludden and the Power7 team accomplished this remarkable feat with a lot of foresight in planning, metrics collection and careful execution. Tight interlocking between metrics collected and verification plan was key part of tracking mechanism and functional closure. This project should serve as an example of how to plan for and manage risks in a complex verification project.

Kudos to John and the IBM team. His full presentation can be downloaded here.

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By Dayna Romanick
Sr. Recruiting Manager
Silicon Elite

There are job openings out there. Companies are looking for innovative ways to fill their needs with a large number of contract to hire or trial periods being offered. Salaries are down markedly and expectations are higher. The majority of companies that are hiring are looking for specific skill sets, hands on experience and a large variety of soft skills. Interns, new grads and less experienced engineers from prestigious schools are being hired by forward thinking, budget conscious companies. Those with many years of experience are finding a new full time direct hire less easily, though they continue to be in demand for contract positions. The key word is flexibility. Your willingness to work with an employer in terms of hours worked, job title and salary all contribute to your employ-ability.

More than ever, engineers will have to prove their worth in 2010. “Companies with highly paid engineers whose skills are not up to date are doing a market reset,” says Karen Panetta of IEEE. This means that engineers must either improve the value they bring or risk being let go. “Some engineers are going back for a master’s degree or a certificate program.”

Will engineers who have been laid off in this recession get back on track in 2010? “If they aren’t evolving their skills, they’ll have a hard time,” Says Panetta.“ Compared to 2009, we think 2010 will be better,” says Kurt Rippelmeyer, industry principal for engineering and energy at staffing firm Yoh. With credit tight, production down and the future unusually uncertain, many firms laid off engineers in 2009.

As the new decade begins, when firms do hire, they will likely place strong hedges on their bets. “The majority of hires in 2010 will be on a contract basis to start,” says Rippelmeyer. “Large engineering firms are going to a new workforce composition of about 20 percent contract. Companies will start to bring folks back on contract.”

Still, some believe an engineering jobs recovery has already begun. “We’ve recently seen a 180-degree turnaround” from the recession’s difficult market for engineers in certain specialties, says Karen Panetta, chair for the IEEE Women in Engineering Committee and associate professor of engineering at Tufts University.

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If you live in the Southern region, the employment picture may improve slightly over the last quarter of 2009 — though there seems to be a flood of people moving to follow the job market (look at license plates when next you’re out). Other parts of the country are not yet ready to see an increase in hiring. Most are facing another round of layoffs, or are looking to replace those who have recently retired. Most companies are now in the budgeting process, and are looking at a brighter time in Q2 and Q3 with funds available for salaries.

There are some great opportunities available for those willing to drop their salary expectations and wear multiple hats. At the moment, project managers are also lead engineers, trainers and QA. There are also opportunities available for experienced professionals willing to travel. New graduates are having a more difficult time finding companies willing to pay premium prices for non experienced staff. There are a large number of new graduates looking to garner experience through internships and entry level positions, some paying as little as minimum wage.

According to the Manpower Employment Outlook Survey:

In the South, 12% of employers surveyed expect to take on more staff, and 10% plan to decrease employee levels, resulting in a Net Employment Outlook of +2%. When seasonal variations are removed from the data, the Quarter 1 2010 employment forecast is slightly weaker compared to one year ago at this time but moderately stronger than Quarter 4 2009. Employers in the South have the strongest Outlook among the four U.S. regions for Quarter 1 2010.

Employers in all 12 industry sectors surveyed in the South anticipate stable or strengthening job prospects for Quarter 1 2010 when compared to Quarter 4 2009.

In Austin specifically, there are a number of start up companies, smaller companies expanding into our market, and industry leaders beginning to look at new engineering needs, as new products are coming to market requiring expertise in multiple areas. Again, companies seem to be looking for candidates with less than 2 years of specific experience or candidates with 7 or more years of hands on engineering expertise. There are few opportunities for those who have moved away from hands on technical skills.

As always, most positions are found through networking. We recommend that you update your resume, highlight your skills, success stories (especially those that show quantifiable money savings) and leadership abilities. Be open to new “non-traditional” proposals of work, such as part time, remote, contract, travel and possible relocation. As always, prepare for your interview, brush up and stay current with your technical and communication skills. Consider practice interviews within your networking groups.

Make sure your resume contains current contact information, both email and phone, and use spell check!

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By Doug Smith of Doulos

Conferences aren’t my favorite events to attend. They tend to be dominated by the big three EDA companies, and the messages are usually just a variation on what was said last year. However, there is always something useful to glean if you listen hard enough, and I think DVCon this year is no exception.

While DVCon is generally more of a verification conference, I found design related topics surprisingly absent. Cliff Cummings presented a good paper on using SystemVerilog’s unique, priority, and 1800-2009′s unique0 constructs, but other than that, everything centered on verification except for some brief discussion on C synthesis at a panel and the SystemC synthesizable subset at the OSCI tutorial session. Verification continues to dominate the industry’s focus as well as high-level modeling.

In fact, I felt that the major topics at DVCon this year were verification methodologies (VMM & OVM), TLM 2.0, and SystemVerilog. I’ll just say a brief word on each.

Both VMM and OVM have recently been updated. Synopsys has added significant features to VMM in their 1.2 release. Doulos sponsored a VMM 1.2 tutorial along with other VMM Central partners highlighting the new features like TLM 2.0 support, implicit phasing, and enhanced testbench structure and configuration as well as explaining how to exploit the RAL register package. In conjunction, Doulos gave away their new VMM 1.2 Golden Reference Guide and has made available a VMM 1.2 tutorial on their website. OVM is also recently updated (version 2.1), but it hasn’t majorly changed so the story is still much the same.

The SystemC NASCUG meeting was co-located with DVCon and there seemed to be a lot of interest around TLM 2.0. OSCI also hosted a TLM 2.0 tutorial session and there was a user paper session centering on TLM. VMM’s TLM 2.0 implementation generated a bit of interest as well. While I don’t use TLM for SystemC modeling, given all the buzz about it I have to conclude that it’s being well-embraced by the industry and it looks like it’s here to stay. I certainly find TLM connections quite useful in an OVM/VMM testbench.

Personally, I found the most interesting papers were those discussing SystemVerilog. Dave Rich from Mentor proposed a multiple class inheritance enhancement, which seems to have great potential. Cliff Cummings talked about enhancing the language to handle X optimism and pessimism. Eduard Cerny discussed new SV-2009 checker and assertion features. But I have to admit, the nagging question I have is, “Will this language everstop exploding?” If I may say, SystemVerilog is like an ever-expanding patchwork, where piece after piece is added but none of it ever seems to truly fit together. And every year, more and more ideas are proposed to enhance it. Oh well, I guess it’s what we have to live with. For those not converted yet to SystemVerilog, my colleague, Alan Fitch, wrote in his DVCon paper, “How to Achieve Sample-Based Coverage Using VHDL” — quite a unique topic among all the other presented papers. Keep an eye out on the Doulos website for the upload of his paper if you’re interested. I usually write papers that show how to work with or around what we already have. That’s why I presented a paper on matching asynchronous behaviors using SystemVerilog assertions (soon to be uploaded to the Doulos website), and likewise, my colleague, John Aynsley, presented a great paper on using the DPI to interface with C/C++ models.

I think the most exciting news at DVCon this year came from Accellera. Accellera’s Verification IP (VIP) technical subcommittee has announced that a universal verification methodology (UVM) is planned for release mid-March. UVM will be based on OVM 2.0.3 and have features of VMM incorporated into it. The amazing thing is that Synopsys, Cadence, and Mentor are all unanimously behind UVM. I think this will definitely reshape the verification methodology story in the industry over the coming year. I was also pleased to hear that the unified coverage interoperability standard (UCIS) is due out in October. This should give us a common way to access and merge all of our coverage data. Lastly, I was rather surprised by the take-away message from Brian Bailey’s panel on minimizing verification time and effort—engineers need more training!! As a trainer, I couldn’t agree more! :)

Doug Smith

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By Richard Goering on February 1, 2010.

This article is reposted from the Cadence blog.

Can verification engineers gain control over the verification process, and stop being full-time firefighters? With proper planning, communication, and organization, the answer is “yes,” according to Allison Goodman, validation program manager at Intel for client and enterprise solid state hard drives.

Goodman spoke at a Silicon Valley DVClub lunch meeting January 26 at Dave and Buster’s restaurant in Milpitas, California. DVClub is an interesting organization. With chapters in Austin, Bangalore, Boston, Dallas, Research Triangle Park, San Diego, and Silicon Valley, the club’s stated purpose is “to have fun while helping build the verification community through quarterly educational and networking events.” IC engineers can join for free, and events are free. Costs are picked up by sponsors, including Cadence.

The January 26 event brought together around 120 attendees. There were a few EDA folks, but as far as I could tell, most attendees were verification engineers. Goodman’s speech was entitled “Tales from the trenches – validation missteps making us full time firefighters.” Goodman started her speech by noting that “it’s not technical problems that cause bad things to happen. It’s usually on the people side.” She identified four “missteps” that force engineers to put out fires rather than proactively validate a product’s quality.

Misstep #1: Insufficient planning

Insufficient planning occurs when you don’t have what you need to do testing, and your test coverage falls short. It’s caused by undocumented assumptions, the increasing scope of projects, and “missed dependencies” (you need 10 prototypes but only get 5). “If you don’t plan for it, it will surprise you, and every surprise will end up as a fire.”

The solution? Put your plan in writing – including who does what, how features work, what it means to be “done,” what checkpoints will monitor progress, and criteria for success. Keeping track of assumptions may be the biggest part of the solution. Write them down!

Misstep #2: Not designing for test

Designers often think their designs won’t have any mistakes, so there’s no plan for testing and no communication with validators. This makes it difficult to find and replicate bugs, to figure out what you need to monitor, and to know when you’re done. Interpreting test results as “pass” or “failure” may be very difficult. The antidote is for validators to get involved in the earliest stages of the design process. “Ask how you’re going to test it and how you’re going to tell if it’s working.”

DVClub provides an opportunity for networking as well as speakers and lunches.


Misstep #3: Not creating and integrating feedback loops

All too often, the marketing team or the design engineers make changes to a product, and don’t communicate those changes to the verification team. Further, many companies place engineers in “silos” with little or no communication – for example, there are software engineers, hardware engineers, and firmware engineers who don’t talk to each other.

What’s needed is continuous feedback about any changes in the product, as well as problems found with the product. Tests should be monitored for effectiveness and continually improved.

Misstep #4: Lack of transparency

Lack of transparency happens when you tell your boss (or team) that everything is well when it really isn’t. Or, you skimp on tests and coverage as schedule pressure rises, and don’t let managers know. As a result, risks and coverage gaps increase. “Tell the real story, and encourage others to do the same. Don’t declare that it’s done until it’s really done.”

My takeaway

While there are tools that can help with verification planning and monitoring – such as Cadence Incisive Enterprise Manager – quality verification depends on “people” factors such as whether and how verification teams plan, how early they’re involved with the design process, how well and how honestly people communicate, and how adaptable teams are to feedback and change. Pay attention to these issues and perhaps you can put the fire extinguishers away.

Richard Goering

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By Dayna Romanick, Sr. Recruiting Manger

Analysis of the Current Job-Market for Semiconductor Engineers

While there are areas of the country that are showing an upswing, we have yet to see the robust hiring intentions that were predicted earlier this year and would be indicative of a full labor market recovery. Seasonally adjusted data reveals only the southern region of the US  showing promise with a slight increase in employer optimism. Western and southwestern parts of the country appear to have somewhat stabilized, and companies based in the northeast are trailing behind with the weakest outlook of all.

Of the more than 28,000 employers surveyed, a significant 69% expect no change in their Q4 hiring plans. Twelve percent anticipate an increase in staff levels while 14% expect a decrease in payrolls, resulting in a Net Employment Outlook of -3% after seasonal adjustment. These are the weakest figures since the survey began in 1962. The final 5% of employers indicated they were undecided about their hiring intentions.1

In the Technical/IT/Engineering fields most companies are waiting until their budgeting processes are complete to determine hiring needs for next year. As we’ve seen in past years, most people hired in Q4 will have actual start dates in Q1 of the following year, although these opportunities are proving to be more sparse than was predicted earlier in Q3.

Looking Forward

Most professionals in the staffing and recruiting industries expect contract positions to be the first key indicator of labor market recovery since many of these position signal the beginning of new projects. In Austin, some layoffs are expected to continue with lack of funding, the inability to borrow money and the widespread availability of less expensive outsourced labor taking a portion of the blame.

Look for opportunities in “newer” technologies and with employers catering to government enterprises. In spite of discouraging figure, opportunities continue to exist for highly-skilled and focused professionals as well as for qualified persons with limited experience ( < 5 yrs) who hold reasonable salary expectations are open to relocation and travel.

Improving Your Chances

At this point, your resume is one of your best assets. This can be a chance for you to document valuable hands on skills, money saving improvements at past companies and other positive impacts that can open doors to an interview. Keeping up to date on new technologies is also an important trait that should not be overlooked. Be sure to present skills that could potentially be useful, even if they’re not in the job requirements. This shows initiative and could differentiate you from countless other applicants.

Remember that resumes should be custom tailored to each position that you are applying for. Thoroughly read the posted job descriptions and requirements of each position, and incorporate these things into your own qualifications, past responsibilities and objective. Cover letters are also important in capturing attention, and your correspondence with potential employers is an excellent place to demonstrate the strength of your interpersonal communication skills. This article gives some solid advice on resume writing principles.

Network with everyone you know in the industry, even if it’s nothing more than keeping in touch on social networking sites. Try writing personalized recommendations for people on LinkedIn (not cut and pasted blurbs), and you may be surprised to see how many people will return the favor.

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By Dayna Romanick
Sr. Recruiting Manager: Silicon Elite

This year remains tough for many job-seekers in the semiconductor industry. Q3 has been marked with leading employers laying off and consolidating work forces in all areas of the semiconductor industry. Although layoffs have declined, salaries of new hires have dropped due to the surplus of labor, and employers are becoming increasingly selective of those who they bring aboard. A recent study by the Society for Human Resource Management (SHRM) shows that 28% of large companies continued layoffs throughout Q3.

However, it’s also important to remember that any statistics you read may possibly be slanted toward the larger companies simply because of their large operational scales. The same SHRM poll showed that only 13% of companies, regardless of size, conducted layoffs in Q3. Small companies and startups are now where the majority of opportunities currently exist. Because of this, attending networking events and staying in tough with old co-workers have become increasingly more important for job seekers.

New grads, or those with less than 2 years experience continue to find positions more easily than those in mid career, and there is a market for designers with mixed signal / analog experience in the audio area. Researchers and process individuals continue to be in demand by fabs, and sales people should find a good marketplace for their skills as well, especially those who have well documented expertise in developing new clients.

Many engineers prepare their resumes with a heavy emphasis on technical experience. While this is certainly important, it can also be beneficial to mention cost savings or additional profits that can be directly attributed to things that you have done. In this economy, it could be the one thing that sets you apart from other candidates of equal qualification.

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The first DVClub “Lunch Around” of 2009 was held yesterday at Jasper’s restaurant in the Domain. “These events are a change from our normal speaker event with 175+ people”, said organizer Eric Hennenhoefer. “Instead we have a series of round-table discussions with about 30 people per event.  This makes it easier share ideas and get to know people better, it’s good to mix it up once a year”.

This year we returned to Jasper’s for two events in North Austin – two more will be held in South Austin at Texas Land and Cattle.  This series is supported in part with the ongoing support of Cadence, Obsidian and Doulos.  Doulos also threw in a few Golden Reference Guides as light reading during dessert.

Among the four tables, discussions were lively and crossed broad number of topics. One table chose to focus on the business side of verification, talking about the fate of Freescale, the changing role of businesses in China, and speculations on the economy. Other tables were more technical in their discussions, concentrating on trends in SoC verification, challenges of verifying floating point units in CPUs, exhaustive simulation and FPGA prototyping. Each table was comprised of five verification engineers with a total of twenty in attendance.

The DVClub “Lunch Arounds” will continue throughout the month of October and will be held once more at Jasper’s on October 22nd. If you’re interested in attending, contact molly@dvclub.org to make arrangements.

Jasper’s in North Austin (at the Domain)
11506 Century Oaks Terrace #128
Austin, TX 78758
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  • Thursday, October 8th
  • Thursday, October 22nd

TX Land & Cattle
1101 S MO Pac Expy,
Austin, TX 78746
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  • Wednesday, October 14th
  • Thursday, October 29th
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    lunch-arounds-1

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