November 2009 Employment Outlook for Design Verification Professionals

November 19th, 2009 by admin

By Dayna Romanick, Sr. Recruiting Manger

Analysis of the Current Job-Market for Semiconductor Engineers

While there are areas of the country that are showing an upswing, we have yet to see the robust hiring intentions that were predicted earlier this year and would be indicative of a full labor market recovery. Seasonally adjusted data reveals only the southern region of the US  showing promise with a slight increase in employer optimism. Western and southwestern parts of the country appear to have somewhat stabilized, and companies based in the northeast are trailing behind with the weakest outlook of all.

Of the more than 28,000 employers surveyed, a significant 69% expect no change in their Q4 hiring plans. Twelve percent anticipate an increase in staff levels while 14% expect a decrease in payrolls, resulting in a Net Employment Outlook of -3% after seasonal adjustment. These are the weakest figures since the survey began in 1962. The final 5% of employers indicated they were undecided about their hiring intentions.1

In the Technical/IT/Engineering fields most companies are waiting until their budgeting processes are complete to determine hiring needs for next year. As we’ve seen in past years, most people hired in Q4 will have actual start dates in Q1 of the following year, although these opportunities are proving to be more sparse than was predicted earlier in Q3.

Looking Forward

Most professionals in the staffing and recruiting industries expect contract positions to be the first key indicator of labor market recovery since many of these position signal the beginning of new projects. In Austin, some layoffs are expected to continue with lack of funding, the inability to borrow money and the widespread availability of less expensive outsourced labor taking a portion of the blame.

Look for opportunities in “newer” technologies and with employers catering to government enterprises. In spite of discouraging figure, opportunities continue to exist for highly-skilled and focused professionals as well as for qualified persons with limited experience ( < 5 yrs) who hold reasonable salary expectations are open to relocation and travel.

Improving Your Chances

At this point, your resume is one of your best assets. This can be a chance for you to document valuable hands on skills, money saving improvements at past companies and other positive impacts that can open doors to an interview. Keeping up to date on new technologies is also an important trait that should not be overlooked. Be sure to present skills that could potentially be useful, even if they’re not in the job requirements. This shows initiative and could differentiate you from countless other applicants.

Remember that resumes should be custom tailored to each position that you are applying for. Thoroughly read the posted job descriptions and requirements of each position, and incorporate these things into your own qualifications, past responsibilities and objective. Cover letters are also important in capturing attention, and your correspondence with potential employers is an excellent place to demonstrate the strength of your interpersonal communication skills. This article gives some solid advice on resume writing principles.

Network with everyone you know in the industry, even if it’s nothing more than keeping in touch on social networking sites. Try writing personalized recommendations for people on LinkedIn (not cut and pasted blurbs), and you may be surprised to see how many people will return the favor.

October 2009 Employment Outlook for Design Verification Professionals

October 19th, 2009 by admin

By Dayna Romanick
Sr. Recruiting Manager: Silicon Elite

This year remains tough for many job-seekers in the semiconductor industry. Q3 has been marked with leading employers laying off and consolidating work forces in all areas of the semiconductor industry. Although layoffs have declined, salaries of new hires have dropped due to the surplus of labor, and employers are becoming increasingly selective of those who they bring aboard. A recent study by the Society for Human Resource Management (SHRM) shows that 28% of large companies continued layoffs throughout Q3.

However, it’s also important to remember that any statistics you read may possibly be slanted toward the larger companies simply because of their large operational scales. The same SHRM poll showed that only 13% of companies, regardless of size, conducted layoffs in Q3. Small companies and startups are now where the majority of opportunities currently exist. Because of this, attending networking events and staying in tough with old co-workers have become increasingly more important for job seekers.

New grads, or those with less than 2 years experience continue to find positions more easily than those in mid career, and there is a market for designers with mixed signal / analog experience in the audio area. Researchers and process individuals continue to be in demand by fabs, and sales people should find a good marketplace for their skills as well, especially those who have well documented expertise in developing new clients.

Many engineers prepare their resumes with a heavy emphasis on technical experience. While this is certainly important, it can also be beneficial to mention cost savings or additional profits that can be directly attributed to things that you have done. In this economy, it could be the one thing that sets you apart from other candidates of equal qualification.

2009 Lunch Arounds at Jasper’s

October 19th, 2009 by admin

The first DVClub “Lunch Around” of 2009 was held yesterday at Jasper’s restaurant in the Domain. “These events are a change from our normal speaker event with 175+ people”, said organizer Eric Hennenhoefer. “Instead we have a series of round-table discussions with about 30 people per event.  This makes it easier share ideas and get to know people better, it’s good to mix it up once a year”.

This year we returned to Jasper’s for two events in North Austin – two more will be held in South Austin at Texas Land and Cattle.  This series is supported in part with the ongoing support of Cadence, Obsidian and Doulos.  Doulos also threw in a few Golden Reference Guides as light reading during dessert.

Among the four tables, discussions were lively and crossed broad number of topics. One table chose to focus on the business side of verification, talking about the fate of Freescale, the changing role of businesses in China, and speculations on the economy. Other tables were more technical in their discussions, concentrating on trends in SoC verification, challenges of verifying floating point units in CPUs, exhaustive simulation and FPGA prototyping. Each table was comprised of five verification engineers with a total of twenty in attendance.

The DVClub “Lunch Arounds” will continue throughout the month of October and will be held once more at Jasper’s on October 22nd. If you’re interested in attending, contact molly@dvclub.org to make arrangements.

Jasper’s in North Austin (at the Domain)
11506 Century Oaks Terrace #128
Austin, TX 78758
View Map

  • Thursday, October 8th
  • Thursday, October 22nd

TX Land & Cattle
1101 S MO Pac Expy,
Austin, TX 78746
View Map

  • Wednesday, October 14th
  • Thursday, October 29th
  • lunch-arounds-1

    lunch-arounds-1

    September 2009 Employment Outlook for Design Verification Professionals

    September 18th, 2009 by admin

    By Dayna Romanick
    Sr. Recruiting Manager: Silicon Elite

    There’s good news in the marketplace if you’re a bit adventurous, startups are hiring. Many experienced DV engineers are leaving behind the security of their established companies in hopes of becoming a part of something that could become the next Google. In fact, recent grads (with less than 3 years of experience) and highly experienced engineers (with >10 years in the field) seem to be in the greatest demand at the moment.

    But why are these people finding work, while so many others continue to struggle? The key here appears to be their hands on nature. Those who have moved away from day to day engineering skills in favor of management are finding it extremely difficult to reposition themselves. Those who have stepped away for a year or two are also finding difficulties in re-entering the marketplace. With the closing of multiple fabs, design centers and the discontinuation of several verification projects, the industry’s unemployment rate is roughly at about 9.8%. This includes the loss of another 8000 jobs last month alone.*

    Although the industry has seen tough times this year, things do appear to be getting somewhat better. Employers are beginning to budget for next year and project the cost of hiring additional engineering personnel, albeit at reduced pay rates. Opportunities are also expected to increase over the coming year with companies specializing in products and services which serve to expedite getting chip designs to market.

    If you’re still looking for a job, you should know that an upturn is predicted in Q4, with even more opportunities surfacing in early 2010. Now is the time to prepare for it by updating your resume and sharpening your selling points as a prospective employee.

    * source: Bureau of Labor Statistics

    DAC 2009 in Review

    August 5th, 2009 by admin

    DAC46_logo

    Written by Brian Bailey for DVClub

    At DAC this year, one of the main themes was ESL but not in the usual sense of it having a lot of promise but little to deliver. This year it had a lot to say in two main categories, the first being high-level synthesis and the second being virtual platforms. Given the main focus of the DVClub, I will only talk about the virtual platforms. Quite a few companies were showing their platforms, including Mentor, Synopsys, CoFluent, CoWare and I am sure there were others. These platforms are at two main levels of abstraction.

    At the higher end are platforms typified by the Synopsys Innovator which are primarily intended for software development, verification and debug. These are loosely timed platforms where speed is one of the primary factors. Then there are the more accurately timed platforms such as the Mentor Vista product which is intended for architectural exploration of the hardware system. Other companies such as Imperas also provide high performance processor models that fit into these platforms. The one thing common to most of them, and the main reason why they were such a force at DAC this year was the introduction of the OSCI TLM 2.0 specification at last years DAC. These platforms can now exchange models (although there are still some minor issues) and that is huge. A lack of models was perhaps the biggest reason why these platforms have not taken off. That roadblock has now essentially been removed.

    Some new companies such as Docea were touting high-level power estimation platforms, and just for completeness, Mentor, Cadence, AutoESL, BlueSpec, Synfora, Forte and I am sure others were showing high level synthesis tools.

    There was a panel session on Tuesday about virtual platforms that was one of the worst DAC panels I have ever sat through. It was supposed to address the issue of if platforms should be virtual, physical or hybrid. Ron Wilson tried hard to make it sound fun and interesting, but this is not a debate topic – we all want models in any form that we can get them in and we want them to play together nicely! End of debate – end of panel – nothing to discuss, just some solid engineering that has to happen.

    On Wednesday, there was a much better conceived workshop on virtual platforms that I had been asked to speak at. The workshop was organized by Soha Hassoun and Larry Lapidas and included lots of interesting talks about platforms at many levels of abstraction and intended for many uses. Over lunch was a panel session that also had some much more interesting discussions. Sadly, I had to leave in order moderate a panel entitled “The Holy Grail of Verification – Coverage Closure”. Any of you who have listened to my DVClub talks will know that I have strong views on that issue, but unfortunately I was moderating so had to keep my mouth shut. Ouch that was difficult!

    TLM 2.0 was finally ratified at DAC this year – I wonder if that will have a similar impact on next years DAC. I am hoping to see many more platforms which are extensible – add timing as a layer, add power as a layer, add X as a layer. Then we will have something that will play through multiple levels of abstraction and start to tie together the whole ESL flow.

    Brian Bailey – keeping you covered
    brian_bailey at acm.org

    Join DVClub on LinkedIn groups

    June 10th, 2009 by admin

    Collaborate, network, and discuss DVClub events with fellow members on LinkedIn groups.

    If you receive our newsletters, then you’re already pre-approved.

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    Microprocessor Test and Verification Conference

    June 10th, 2009 by admin

    Preliminary Call for Papers:

    10th International Workshop on Microprocessor Test and Verification (MTV 2009)
    December 7-8, 2009, Hyatt Regency On Town Lake, Austin, Texas, USA.

    Website: http://mtv.ece.ucsb.edu/MTV/

    This is the 10th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross- examination of test and verification experiences and innovative solutions. MTV has been held in Austin for the last 8 years, so please plan on participating in order to make this another successful forum.

    Purpose

    The purpose of this workshop is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa.

    Topics

    AREAS OF INTEREST include, but not limited to:

    • Validation of microprocessors and SOCs
    • Test/Verification of multimedia processors
    • Performance testing
    • High-level test generation for functional verification
    • Emulation techniques
    • Silicon debugging
    • Formal techniques and their applications
    • Verification coverage
    • Test Generation at the transistor level
    • Equivalence checking of custom circuits
    • ESL Methodology
    • Virtual Platforms
    • Software verification
    • Circuit level verification
    • Switch-level circuit modeling
    • Timing validation techniques
    • Path analysis for verification or test
    • Design error models
    • Design error diagnosis
    • Design for Testability or Verifiability
    • Optimizing SAT procedures with applications to testing and formal verification

    Important dates

    Submission: Sept 1, 2009
    Notification: Oct 1, 2009
    Final version due: Nov 1, 2009

    Knowing When Verification is Complete

    March 27th, 2009 by admin

    Introduction

    This article presents an overview of functional design verification using a coverage driven methodology while attempting to answer the question of how much testing is enough. The part being verified in this case will be a general purpose microprocessor, such as those found in mobile computing devices. Note that an approach of this magnitude is not always required. Designs with very limited instruction sets or highly restricted functionalities may be satisfied by simply writing directed assembly code tests to verify their intended functionalities.

    Comparison of Simple and Complex Architectures

    Figure 1 depicts a simple architecture as compared to a complex one. Note that the number of corner cases and unpredictability of the verification space increases as the architecture gains complexity. Thus, the complexity of the architecture determines how much testing will need to be accomplished to properly verify the component’s function.

    Figure 1. Comparison of Verification Spaces

    Comparison of Verification Spaces

    Measuring Verification Progress

    Coverage metrics are the dominant method for measuring verification progress in the industry today. Coverage points are normally designated by the design engineers looking at the logic of their block and by verification or system engineers looking at the functional definition of the part. Both of these are critical insights into the required verification coverage of the design.

    Coverage points, indicated by the red dots in Figure 2, are deliberately chosen with respect to placement and density according to design knowledge and risk assessment.

    Figure 2. Distribution of Coverage Points

    Distribution of Coverage Points

    Directed Testing

    In the past, directed tests were typically written to hit coverage points. Because directed tests are by their very nature highly targeted and relatively inflexible, this resulted in much of the design not being tested as is shown by the ratio of red to gray in Figure 5. In addition to the low overall coverage that results from this approach, creation of directed tests is time consuming and requires highly skilled engineers. In this approach, testbench checkers that detect hits to coverage points are often overlooked with the assumptions that the engineers writing the tests know how to hit the required coverage points and that human errors will not be significantly problematic. In addition, as the design changes over the course of development, the directed test may lose track of its target coverage point. Without coverage monitors, these types of errors will not be detected and the design will not be as thoroughly verified as it appears to be on paper.

    Using a Random Test Generator to Close Coverage

    As processor designs became more complex, the need to hit more coverage points became apparent. Once the grid has been established, large numbers of purely random tests may be incorporated to begin closing coverage. Some of these tests may hit points on the coverage grid while others will not.

    Figure 3. Intersection of Coverage Grid and Pure Random

    Intersection of Coverage Grid and Pure Random

    Approaching the problem of hitting coverage points from a random test generator viewpoint, a single engineer begins by writing a few generator templates and then generates tests using those templates. The generated tests are then run on a testbench which incorporates coverage monitors. The coverage monitors report all coverage points that are hit by the tests. As long as tests generated from the templates continue to hit new coverage points, the templates are kept in the nightly suite. As the rate of hitting new coverage points declines, new generator templates are created to target coverage holes. This approach requires skilled engineers to write checkers for the testbench but less skilled engineers to run the test generator.

    Directed-random templates are created around points not hit by the purely random templates. We now begin to see the coverage grid closing more tightly (around 95%), and the verification process comes closer to completion.

    Figure 4. Coverage Grid, Directed Random and Pure Random

    Coverage Grid, Directed Random and Pure Random

    Hitting Corner Cases

    Not all coverage points will be hit by fully random or directed random templates. Some coverage points require a long series of events before the targeted behavior takes place. In this case, there are two possible approaches: write directed tests and write directed templates. Probably both of these approaches should be used. Directed tests can get to these most difficult coverage points more quickly but prove only one or a few cases around that point. Directed templates take more time to create but can be written to allow as much random behavior around the coverage point as possible.

    Figure 5. Review Templates and Relax Restrictions

    Review Templates and Relax Restrictions

    Finally, existing tests are reviewed, and as much directed behavior as possible is removed before the tests are run again. Coverage then reaches full closure, and these tests are run until the schedule no longer permits.

    Bailey on Verification at the Club

    March 23rd, 2009 by admin

    By Grant Martin
    This blog post originally appeared at:
    http://www.chipdesignmag.com/martins/2009/03/19/bailey-on-verification-at-the-club/
    — March 19, 2009 @ 11:14 pm

    Today I attended the latest meeting of the Silicon Valley branch of the DVClub. For those not familiar with the DVClub (DV = Design Verification), it was started by Eric Hennenhoefer in Austin a few years ago. It now has branches in Austin, Bangalore, Boston, Bristol, Dallas, RTP, San Diego and Silicon Valley. In Silicon Valley it meets about once a quarter for a talk on some aspect of verification. I first heard of this about 1.5 years ago when we were invited from Tensilica to give a talk about verifying our video subsystem. The club has all the right ingredients to attract a crowd of engineers:

    1. a free lunch
    2. interesting speakers
    3. did I mention a free lunch?
    4. a chance to meet new colleagues and old friends
    5. and of course, a free lunch

    (Sponsors such as Cadence, Doulos, Denali, Silicon Elite and Obsidian pick up the tab for the venue and lunch (updated after original post, on Friday 20 March 2009, to correct list of sponsors)).

    Today’s speaker was Brian Bailey, a friend and co-author of mine, speaking on “Is it time to declare a verification war?” The place was packed out with about 130 people, filling the room to capacity (Eric said this was the largest Silicon Valley DVClub crowd to date).

    Brian Bailey

    Brian Bailey

    Brian spoke about his philosophy of verification, drew some analogies to Sun-Tzu’s Art of War, and also spoke about three technologies that he felt had potential to change verification significantly:

    1. Functional Qualification – as exemplified by Certess (now SpringSoft) Certitude
    2. Raising abstraction – as exemplified by Calypto’s sequential equivalence checking
    3. “Intelligent testbenches” – as exemplified by Jasper’s Behavioural Indexing

    Brian’s slides are available here.

    IF you live or work anywhere any of these branches of the DVClub, and have an interest in verification, I recommend that you check them out. Sign up for their newsletter and get notified of meetings in advance.

    Random Test Generator Taxonomy

    February 27th, 2009 by admin

    There is a vast landscape of test generators used in the industry today. These range from simple scripts and parameterized macros that can be created in a matter of weeks to full featured systems used by cutting edge processor verification teams.

    In many cases, a processor design team will select a simple test generator for the first project and gradually evolve it into a more advanced form as the architecture matures. This continual evolution of test generator technology stems from several causes:

    • Earlier designs tend to be simpler with later revisions adding more features and complexity.
    • Later designs may prove complex enough to require a new approach.
    • The verification effort may initially be underestimated.
    • Estimates become more realistic over time as they become based on knowledge gained in earlier revisions.
    • Products that go through several revisions and enhancements are likely to be those that have proven successful in the market and these tend to have better funding for both design and verification.

    Table Based Generators

    Table based test generators are the simplest generators available. Creation of such generators can be accomplished relatively quickly, and maintenance requirements are often low. These generators work by capturing ISA knowledge and storing it in a central table for later use. Because of their simplistic nature, table based generators may be used by less skilled personnel to create interesting tests. There is a drawback to these generators however, as their implementation is generally restricted to simple architectures. Usage on more complex ISAs may result in an inability to reach corner-cases or create complex scenarios. Table based generators may also generate invalid tests at times.

    Static Generators

    Static generators are similar to table based generators with the exception that the majority of the instruction, operand and data selection reside in complex procedural code. Static generators are capable of producing more random behavior than table based generators, but still have trouble
    hitting many corner-cases. In addition, the skill level required to create and maintain such a tool rises sharply once this level of sophistication is reached.

    Dynamic Generators

    Dynamic generators incorporate significant knowledge about the architecture being tested. They enhance the ability of less-skilled users to generate complex tests that can hit hard-to-reach corner cases without stumbling on subtle programming pitfalls. This added knowledge, flexibility and ease-of-use is reflected in a more complex generator and consequently the cost of creating and maintaining the generator are greater than for table-based or static generators.

    Comparison of Various Aspects of Random Test Generators