Our next DVClub event will be on “Assertion-Based Verification” in September. We are also planning a one-day UK verification conference in November. We have a number of international speakers already lined up – please help us choose the location (click here).

Finally – if you are interested in multicore then registration on our next one day conference (on “Programming Multicore Systems” on 5th Sept in Bristol) is now open – and it is free to attend.

Regards,

Mike

Assertion-based verification has many advantages, but is not particularly easy to use. At Silicon Valley DVClub April 26, two engineers discussed the benefits and challenges of assertions, and described their experience with two tools that help answer the question, “who’s going to write all those assertions?”

DVClub (Design Verification Club), co-sponsored by Cadence, presents free educational and networking events at various locations in the U.S., Europe, and India. Presenters at the Silicon Valley DVClub luncheon were Jing Li, verification engineer at Broadcom, and Eric Deal, president of silicon IP provider Cyclic Design.

Li described Broadcom’s experience with BugScope, an “assertion synthesis” tool from NextOp Software, while Deal described his experience with Zazz, a tool from Zocalo that helps users create and debug SystemVerilog assertions. (Both companies are Cadence partners and both tools are closely integrated with the Cadence Incisive simulation environment. Last year I ran Industry Insights Q&A interviews with Yunshan Zhu, CEO of NextOp, and Howard Martin, president of Zocalo).

Broadcom: Challenges of Assertions

Li described a “traditional” verification flow at Broadcom that includes block-level testing, coverage signoff, subsystem testing, chip-level testing, and emulation. While this flow has been quite successful, she noted that “as design complexity increases, we’re finding bugs later than what we’d like to see. It’s an indication we need to improve the methodology so that at each level of verification, we have more visibility into what is being tested.”

Assertion-based verification (ABV) can provide that visibility, but has not been part of the Broadcom flow because “we have some issues that couldn’t be solved.” Li identified the following problems:

• Learning the SystemVerilog assertion (SVA) language and mastering assertion coding is difficult for engineers
• Assertions are time-consuming to debug
• Assertions may not directly match designer intent, resulting in false failures in simulation
• There’s no good way to measure the quality of hand-generated assertions
• It’s unclear how many assertions one needs to write
• Assertion reuse is a problem, with new assertions often needed even for small design changes

These challenges led Broadcom to evaluate BugScope. Li described how it automatically generates assertions based on regressions, and how designers then evaluate assertions to determine which are “true” assertions and which are functional coverage properties.

“We found that using this assertion synthesis technology helps improve the quality of block-level verification,” Li said. “For almost every block for which we tried BugScope, we were able to find bugs, and most of those bugs could not be found with the old flow. And we were able to find bugs even during the property review process.” All this is possible with very little change to the existing verification flow, she said.

Li provided four examples of bugs found with BugScope that would not have been detected without assertion synthesis. She described a bug that was found without running any tests at all, a bug hiding in a functional coverage hole, a bug that was not detected with manually generated assertions, and a bug that appeared only in emulation and could not be replicated with simulation or formal verification.

However, she also listed some improvements Broadcom would like to see, including generation of assertions for cross-module bugs, a GUI for the assertion classification process, and better performance with large numbers of instances. BugScope, she concluded, is “now officially part of our signoff criteria and is really increasing our verification confidence.”

Cyclic Design: Assertions for IP Verification

Eric Deal brought a different perspective to the DVClub meeting – he’s a designer, and he’s president of a company that specializes in error correction (ECC) IP for NAND flash. He’s long been a believer in ABV, and he noted a number of advantages of assertions. He said they can cut debug time, improve designer-to-verification engineer communications, document design behavior, detect unobservable faults, and ease integration of IP modules. On this last point, he said that assertions “really provide a lot of added value to my customers.”

Deal started using the Open Verification Library (OVL) some years ago when it was being standardized by Accellera. While easy to use, the assertions are simple and inflexible, and result in “messy” code when they get instantiated into modules. Then he learned SVA, and found that it provided more power and flexibility. However, he noted, it’s difficult to construct “anything beyond relatively simple assertions” with SVA.

Approached by a founder of Zocalo, Deal evaluated an early version of Zazz. The product has two big advantages, he said. First, its graphical Visual SVA environment makes it possible to create complex assertions without becoming an expert in SVA syntax. Secondly, and perhaps most importantly, Zazz provides a way to debug assertions at the time of creation. It does this by effectively creating a constrained-random testbench around each assertion, and generating a pass or fail waveform.

The impact on Cyclic Design? “It improved my internal verification and debug time by quickly identifying both the time and location of errors in simulation,” Deal said. Today the company ships assertions with its IP. The assertions help customers find problems in ports and interfaces, and provide insights not covered in the user’s guide. But customers must be educated to turn the assertions on.

Conclusion

Assertions are a powerful tool for designers and verification engineers, but writing assertions is a pain. For this reason tools from NextOp and Zocalo have attracted a good deal of interest. There’s no better way to learn about them than to hear directly from the users. Thus, I think this DVClub presentation was very timely. See the DVClub web site for information about upcoming presentations in various cities.

Richard Goering

DVClub is a professional networking organization which provides quarterly lunch events for semiconductor designers and verification engineers. The organization currently has active chapters in four U.S. cities as well as international chapters in Bristol, Bangalore, Eindhoven and Toronto.

“2011 is shaping up to be a great year for DVClub”, said founder Eric Hennenhoefer. “The support of the community in expanding local DVClub chapters has been unprecedented.” Hennenhoefer is an Austin entrepreneur and currently serves as CEO of Obsidian Software, a sponsoring entity of DVClub in the US.

International DVClub chapters are run by local event organizers who secure sponsorships, select venues, and presenters for events. For information about starting a local DVClub chapter in your city, please contact admin@dvclub.org

Contacts:

DVClub Austin

Eric Hennenhoefer

DVClub Delhi

Anupam Bakashi

The goal of DVClub events is to help build the verification community through quarterly educational and networking functions. We currently have active branches in Austin, Boston, RTP and Silicon Valley as well as international branches in Europe and India.

Events generally involve a free lunch followed by a technical program
and time allocated for networking. Topics vary, but the core focus is
end user verification stories, verification technology, and speculation
on our chosen career paths.

For more information on becoming a presenter, please contact us at: admin@dvclub.org

Attending MTV was quite a unique experience. It was a pleasant surprise to find that the audience at MTV workshop was very diverse. People had come from all around the world to participate in this conference.  The presenters were very approachable, allowing for more valuable feedback during the presentations and conversations than some of the larger conferences.

– Po-Hsien Chang, PhD Student at UC Santa Barbara (ECE)

I enjoyed this workshop and the presentations. Honestly, finding out about papers can be also done by searching in websites like ieeexplore, but the most valuable thing I gained in this workshop was to communicate with people and knowing more about their research interests. I also think that attending such workshops by academic people and people from industry can fill the gap between industry needs and university research.

–Ratika Goyal, Hardware Engineer at Oracle

As a listener, I got so much interesting information, which not only broadened my understanding of the research in this area, but also showed me an almost new world for further study and research.

– Jifeng Chen, PhD Student at the University of Connecticut (EE)

At MTVCon, I was able to attend conference presentations, meetings, and tutorials/workshops at the Design Verification Club (DVClub) that catered to all of my interests while opening the door to many other topics within verification and debugging (with which I am not as familiar). I enjoyed the diverse mix of academic and industry organizations and groups represented at the conference.  Few conferences provide presentations with such detail and insight.

–Patricia Lee, PhD Student at UC Irvine (CS)

Read more about their take on the technical presentations on the Obsidian Blog.

Greg Smith, Sr. Verification Manager at Oracle

Abstract:
So much of today’s metrics used to gauge the progress of a verification project are backwards looking – telling us what ground we have covered. In addition, many metrics commonly in use are subjective and prone to human errors of omission.  I would like to present a different approach to DV project metrics using bug arrivals to actually provide some predictive capability as well as aid in overall project planning.

Download the Presentation Here
Download the “Sample Metrics” File Here

High Performance Collection of Coverage Metrics Using a Relational Database Backend

James Roberts, Sr. Verification Engineer at Oracle

Abstract:
A database is an ideal medium for collecting and analyzing coverage. At Oracle, we marry our Oracle database with coverage collection of our verification, and then use SQL to extract coverage metrics on-demand. This presentation outlines an intuitive scheme for database collection of coverage, and presents data showing the scalability and the high bandwidth this scheme is able to handle.

Download the Presentation Here

“Advanced methodologies used for top-level verification of mixed signal products”, Roger Witlox, Sr. Verification Engineer, PL Integrated IVN & FlexRay, NXP
PDF Slides

The described verification approach is used to verify IC’s that are used in automotive in-vehicle networks. Examples are LIN, CAN and Flexray transceivers. Transceivers are mixed signal designs that translate a digital signal into an analog signal and vice versa and are used in the physical layer of a network. Due to trends like power modes, digital trimming, auto calibration and integration these mixed signal designs are becoming more and more complex. As a result a commonly used architecture contains a central digital state-machine that controls the surrounding analog modules. This all requires a more advanced overall verification approach.

One of the instruments used in this overall verification approach is top-level (chip-level) verification. The goal of top-level verification is to prove interconnect and interoperability. It assumes that functionality is verified at IP-level. The types of bugs hunted with this approach include: wrong polarity, flipped busses and chicken & egg problems. Top-level is always subject to late design changes and often timing critical towards tape-out, therefore the following methods are used: Self-checking, Modeling, Reusability and Functional coverage.

“Analogue Behavioural Modelling: An Inconvenient Truth”, Dave Wiltshire, Texas Instruments, UK
PDF Slides

The complexity of SERDES designs has resulted over several years in increased analogue complexity. This extra complexity means that simple behavioural models cannot be used to test everything in a design. This presentation will discuss the different strategies that have been developed with the TI SERDES design team solve the problem of verifying a complex mixed signal design using Verilog simulators. The following development strategies will be used.
Using standard digital verilog simulation:

• Model analogue behaviour using verilog reals
• Solving how to pass verilog reals across module boundaries
• Migrating to VerilogA behavioural models
• Verifying that the models match the transistor implementation
• Solving the simulation speed issues (wreal)

“Using assertions in AMS verification”, Scott Little, AMS Verification Engineer, Freescale
PDF Slides

Assertions have been used successfully in digital verification methodologies for a number of years. As the size and complexity of AMS blocks and SoC designs increase, there is an increasing need for assertions capable of specifying and checking AMS behaviors. We discuss ongoing work within Freescale and the Accellera AMS Assertions sub-committee to develop, standardize, and deploy AMS assertions.

Verification Tutorial I – Stick a Fork in it: Applications for SystemVerilog Dynamic Processes

Focus: Verification and modeling
Audience: Verification engineers, but designers may find interesting
Skill level: Basic to Advanced Verilog/SystemVerilog

Description: In Verilog, processes come in the static form of always and initial blocks, concurrent assignments, and the fork..join statement. SystemVerilog introduces dynamic processes in the form of new fork..join statements and the std::process class. This presentation explores several applications for dynamic processes in verification and behavioral modeling such as how verification methodologies create independently executing components and control simulation phasing, isolating random number generators for test reproducibility, parallelizing testbench interaction with DPI code, and a way of using dynamic processes with SystemVerilog interfaces to create bus resolution functions and model analog behavior.

Verification Tutorial II – Getting Started with OVM (UVM)

Focus: Verification
Audience: Designers and verification engineers adopting or considering OVM (UVM)
Skill Level: Intermediate – recommended knowledge of class-based SystemVerilog

Description: Basic introduction to OVM. Simple environment presented showing the steps and code required to create an OVM (UVM) testbench environment.

Verification Tutorial III – Introduction to SystemVerilog Assertions (SVA)

Focus: Verification
Audience: Design and verification engineers
Skill Level: Basic – no SystemVerilog required, but some an HDL recommended

Description: Basic introduction to the SystemVerilog assertion language. Intended for those who have no knowledge of SVA and interested in what it’s all about.

Scope

The purpose of MTV is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa. This is the 11th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross-examination of test and verification experiences and innovative solutions.

Areas of Interest include

* Validation of microprocessors and SOCs
* Experiences on test and verification of high performance processors and SOCs
* Test/verification of multimedia processors and SOCs
* Performance testing
* High-level test generation for functional verification
* Emulation techniques
* Silicon debugging
* Formal techniques and their applications
* Verification coverage
* Test generation at the transistor level
* Equivalence checking of custom circuits at the transistor level
* ESL Methodology
* Virtual Platforms
* Software verification
* Circuit level verification
* Switch-level circuit modeling
* Timing verification techniques
* Path analysis for verification or test
* Design error models
* Design error diagnosis
* Design for testability or verifiability
* Optimizing SAT procedures for application to testing and formal verification

Advance Program

2010 Advance Program (PDF)

Registration

IEEE Online Registration Link: click here
If you are unable to use the above link please use this PDF