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analog automation analog verification Architecture ASIC Brian Bailey Cadence checkers C model Complex Architectures corner cases coverage coverage driven methodology coverage grid Coverage metrics coverage monitors DAC Dave Whipp Debugging Design design entry designers' guide consulting digital verification directed assembly code tests directed testing Distribution of Coverage Points Doug Smith Doulos DVClub DVCon emulation Eric Hennenhoefer ESL formal verification functional design verification functional verification general purpose microprocessor modeling OVM RTL testbench SystemVerilog Technical Review UVM Validation Verification verification jobs
Category Archives: Technical Review
Posted on February 20, 2009 by admin
Anyone who has worked on a microprocessor design in recent years knows that verification has become a larger and larger share of the effort to bring a product to market. Designs are becoming increasingly complex and this complexity is often … Continue reading →
Posted in Technical Review
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Tagged emulation, hardware based verification, RTL emulator hybrid, RTL testbench, verification completion, verification platforms
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Posted on November 14, 2008 by eric
Joseph Hupcey of Cadence reviews Dr. Henry Chang’s presentation on analog and mixed signal verification. Continue reading →
Posted in Technical Review
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Tagged analog automation, analog verification, Cadence, design entry, designers' guide consulting, digital verification, Henry Chang, interface errors, Joseph Hupcey, RTL verification, schematic capture
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Posted on October 2, 2008 by eric
Eric reviews John Ludden’s verification strategy for IBM’s POWER6 architecture and discusses the complexity of verifying a modern in-order processor. Continue reading →
Posted in Technical Review
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Tagged High Frequency, IBM, In Order, infinite state, John Ludden, MP/SMT, MT, Out of Order, POWER5, POWER6, RAS, Simultaneous Multi Threading, SMT, Software Simulation, Verification
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Posted on August 28, 2008 by admin
This blog explores the theories of NVIDIA’s Dave Whipp on restructuring DV workflow by using C models in place of the natural language specification. Continue reading →
Posted in Technical Review
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Tagged Architecture, ASIC, C model, checkers, Dave Whipp, Debugging, Design, ESL, Methodology, NVIDIA, Spec, testbench, Validation, Verification
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