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analog automation analog verification Architecture ASIC Brian Bailey Cadence checkers C model Complex Architectures corner cases coverage coverage driven methodology coverage grid Coverage metrics coverage monitors DAC Dave Whipp Debugging Design design entry designers' guide consulting digital verification directed assembly code tests directed testing Distribution of Coverage Points Doug Smith Doulos DVClub DVCon emulation Eric Hennenhoefer ESL formal verification functional design verification functional verification general purpose microprocessor modeling OVM RTL testbench SystemVerilog Technical Review UVM Validation Verification verification jobs
Category Archives: Technical Review
Posted on May 10, 2011 by saturday
D&V engineers are always on the look out for new tools to help rapidly create assertions for ABV. In this video, NextOp’s Yuan Lu talks about a real life case study of the “BugScope” tool in action, as described in … Continue reading →
Posted on April 28, 2011 by saturday
Re-posted from Cadence Industry Insight Blog Original Article by Richard Goering on April 26, 2011 Assertion-based verification has many advantages, but is not particularly easy to use. At Silicon Valley DVClub April 26, two engineers discussed the benefits and challenges … Continue reading →
Posted on June 24, 2010 by saturday
We thought that it might make for interesting reading to compile a list of the most downloaded presentations from past DVClub events. For those of you unfamiliar with DVClub, membership is free and is open to all non-service provider semiconductor … Continue reading →
Posted on May 20, 2010 by saturday
By Hemendra Talesara Complexity In his recent presentation discussing verification of the Power7 processor, John Ludden of IBM opened with a quote from an IBM exec more than a decade ago. “it’s not rocket science”- a perception held by some … Continue reading →
Posted in Austin, Design Verification, Technical Review
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Tagged Architecture, checkers, Complex Architectures, functional design verification, functional verification, RTL testbench, Technical Review, Verification
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Posted on April 14, 2010 by saturday
In his recent Silicon Valley presentation, Bob Colwell referenced several interesting books to validate his points. We’ve already begun receiving emails asking for a list of these titles, so we thought that it would make a great blog posting. Happy … Continue reading →
Posted on March 5, 2010 by admin
By Doug Smith of Doulos Conferences aren’t my favorite events to attend. They tend to be dominated by the big three EDA companies, and the messages are usually just a variation on what was said last year. However, there is … Continue reading →
Posted in DV Conferences, Technical Review
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Tagged Brian Bailey, Cadence, Design, Doug Smith, Doulos, DVCon, Mentor, modeling, OVM, Synopsys, SystemC, SystemVerilog, UVM, VMM
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Posted on February 11, 2010 by admin
By Richard Goering on February 1, 2010. This article is reposted from the Cadence blog. Can verification engineers gain control over the verification process, and stop being full-time firefighters? With proper planning, communication, and organization, the answer is “yes,” according … Continue reading →
Posted in Boston, Silicon Valley, Technical Review
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Tagged Allison Goodman, Validation, Verification
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Posted on March 27, 2009 by admin
This article presents an overview of functional design verification using a coverage driven methodology while attempting to answer the question of how much testing is enough. Continue reading →
Posted in Technical Review
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Tagged checkers, Complex Architectures, corner cases, coverage driven methodology, coverage grid, Coverage metrics, coverage monitors, directed assembly code tests, directed testing, Distribution of Coverage Points, functional design verification, general purpose microprocessor, mobile computing, random test generator, RTL testbench, Verification Progress
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Posted on March 23, 2009 by admin
By Grant Martin This blog post originally appeared at: http://www.chipdesignmag.com/martins/2009/03/19/bailey-on-verification-at-the-club/ — March 19, 2009 @ 11:14 pm Today I attended the latest meeting of the Silicon Valley branch of the DVClub. For those not familiar with the DVClub (DV = … Continue reading →
Posted in Silicon Valley, Technical Review
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Tagged Brian Bailey, DVClub, Eric Hennenhoefer, Is it time to declare a verification war?, Silicon Valley, Technical Review
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Posted on February 27, 2009 by admin
There is a vast landscape of test generators used in the industry today. These range from simple scripts and parameterized macros that can be created in a matter of weeks to full featured systems used by cutting edge processor verification … Continue reading →
