Greg Smith, Sr. Verification Manager at Oracle

Abstract:
So much of today’s metrics used to gauge the progress of a verification project are backwards looking – telling us what ground we have covered. In addition, many metrics commonly in use are subjective and prone to human errors of omission.  I would like to present a different approach to DV project metrics using bug arrivals to actually provide some predictive capability as well as aid in overall project planning.

Download the Presentation Here
Download the “Sample Metrics” File Here

High Performance Collection of Coverage Metrics Using a Relational Database Backend

James Roberts, Sr. Verification Engineer at Oracle

Abstract:
A database is an ideal medium for collecting and analyzing coverage. At Oracle, we marry our Oracle database with coverage collection of our verification, and then use SQL to extract coverage metrics on-demand. This presentation outlines an intuitive scheme for database collection of coverage, and presents data showing the scalability and the high bandwidth this scheme is able to handle.

Download the Presentation Here

Verification Tutorial I – Stick a Fork in it: Applications for SystemVerilog Dynamic Processes

Focus: Verification and modeling
Audience: Verification engineers, but designers may find interesting
Skill level: Basic to Advanced Verilog/SystemVerilog

Description: In Verilog, processes come in the static form of always and initial blocks, concurrent assignments, and the fork..join statement. SystemVerilog introduces dynamic processes in the form of new fork..join statements and the std::process class. This presentation explores several applications for dynamic processes in verification and behavioral modeling such as how verification methodologies create independently executing components and control simulation phasing, isolating random number generators for test reproducibility, parallelizing testbench interaction with DPI code, and a way of using dynamic processes with SystemVerilog interfaces to create bus resolution functions and model analog behavior.

Verification Tutorial II – Getting Started with OVM (UVM)

Focus: Verification
Audience: Designers and verification engineers adopting or considering OVM (UVM)
Skill Level: Intermediate – recommended knowledge of class-based SystemVerilog

Description: Basic introduction to OVM. Simple environment presented showing the steps and code required to create an OVM (UVM) testbench environment.

Verification Tutorial III – Introduction to SystemVerilog Assertions (SVA)

Focus: Verification
Audience: Design and verification engineers
Skill Level: Basic – no SystemVerilog required, but some an HDL recommended

Description: Basic introduction to the SystemVerilog assertion language. Intended for those who have no knowledge of SVA and interested in what it’s all about.

Scope

The purpose of MTV is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa. This is the 11th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross-examination of test and verification experiences and innovative solutions.

Areas of Interest include

* Validation of microprocessors and SOCs
* Experiences on test and verification of high performance processors and SOCs
* Test/verification of multimedia processors and SOCs
* Performance testing
* High-level test generation for functional verification
* Emulation techniques
* Silicon debugging
* Formal techniques and their applications
* Verification coverage
* Test generation at the transistor level
* Equivalence checking of custom circuits at the transistor level
* ESL Methodology
* Virtual Platforms
* Software verification
* Circuit level verification
* Switch-level circuit modeling
* Timing verification techniques
* Path analysis for verification or test
* Design error models
* Design error diagnosis
* Design for testability or verifiability
* Optimizing SAT procedures for application to testing and formal verification

Advance Program

2010 Advance Program (PDF)

Registration

IEEE Online Registration Link: click here
If you are unable to use the above link please use this PDF

We think that the topic is super-interesting, so we’ve provided some preliminary reading material on the subject.

If you haven’t already registered to attend the presentation, we recommend doing so while there are still spots available.

• Hierarchical Simulation-Based Verification of Anton, a Special-Purpose Parallel Machine (PDF)
• A Conversation with David E. Shaw (PDF)
• Grand Challenge: Millisecond-scale Molecular Dynamics Simulations (PDF)
• Slashdot – Supercomputer Sets Protein Folding Record
• Wikipedia – Anton (Computer)

JOB POSTINGS UPDATED – OCT 29, 2010

“We try to help local leaders wanting to start their own chapter wherever we can”, said DVClub founder Eric Hennenhoefer.  “We strive to accomodate the local organizers with some basic infrastructure needs and connect them with the right people.”

“At an earlier period in my career not long ago, guys in my team loved to attend the events in Boston”, said Bakashi. “I think that there is a great need for DVClub New Delhi. I have talked with a few local industry veterans and potential sponsors, and I think that there is a good momentum.”

Individuals interested in attending upcoming events may sign up for the New Delhi mailing list and receive information on future events as it becomes available.

The application deadline for the MTV Scholarship Program is now less than 30 days away. This scholarship will provide round-trip airfare, conference registration fees, and hotel accommodations for several students across the nation to attend the 11th annual workshop on Microprocessor Test and Verification in Austin, TX.

“It’s always difficult to have to choose applicants”, said Eric Hennenhoefer, President of Obsidian Software. “There are so many talented young engineers out there, and we like to help really determined and motivated individuals whenever we come across them.”

2010 marks the first year of this scholarship, which is open to applicants until October 1st. More information can be found by visiting the scholarship program page:

2010 Microprocessor Test and Verification Scholarship

The Chapter Organizer for Eindhoven is Maarten Arts, who is now driving functional verification at Silicon Hive in Eindhoven. The newly established chapter is intended to serve the local verification community from organizations such as NXP, Virage and others.

The Eindhoven and Bristol chapters are expected to collaborate on future events via remote access, which has been a feature of the Bristol chapter since 2009.

For more information on getting involved with DVClub Eindhoven, visit the city page on the DVClub website or contact Maarten Arts for specific questions and information on sponsorship opportunities.

The notoriety of DVClub is spreading organically by word of mouth – something that’s not easy to achieve among a community of engineers. “We continually see new people at each event” said DVClub founder and organizer Eric Hennenhoefer. “Once they’ve experienced a DVClub event, they tend to come back to future events and bring more co-workers with them”. The average quarterly growth rate for DVClub in 2010 has been around 7% per quarter and climbing.

About DVClub:

The principal goal of DVClub is to have fun while helping build the verification community through quarterly educational and networking events. Currently over 50 advisors actively keep the club organized by brainstorming on topics, tracking down speakers, promoting events, and helping out on event day.