The goal of DVClub events is to help build the verification community through quarterly educational and networking functions. We currently have active branches in Austin, Boston, RTP and Silicon Valley as well as international branches in Europe and India.

Events generally involve a free lunch followed by a technical program
and time allocated for networking. Topics vary, but the core focus is
end user verification stories, verification technology, and speculation
on our chosen career paths.

For more information on becoming a presenter, please contact us at: admin@dvclub.org

Attending MTV was quite a unique experience. It was a pleasant surprise to find that the audience at MTV workshop was very diverse. People had come from all around the world to participate in this conference.  The presenters were very approachable, allowing for more valuable feedback during the presentations and conversations than some of the larger conferences.

– Po-Hsien Chang, PhD Student at UC Santa Barbara (ECE)

I enjoyed this workshop and the presentations. Honestly, finding out about papers can be also done by searching in websites like ieeexplore, but the most valuable thing I gained in this workshop was to communicate with people and knowing more about their research interests. I also think that attending such workshops by academic people and people from industry can fill the gap between industry needs and university research.

–Ratika Goyal, Hardware Engineer at Oracle

As a listener, I got so much interesting information, which not only broadened my understanding of the research in this area, but also showed me an almost new world for further study and research.

– Jifeng Chen, PhD Student at the University of Connecticut (EE)

At MTVCon, I was able to attend conference presentations, meetings, and tutorials/workshops at the Design Verification Club (DVClub) that catered to all of my interests while opening the door to many other topics within verification and debugging (with which I am not as familiar). I enjoyed the diverse mix of academic and industry organizations and groups represented at the conference.  Few conferences provide presentations with such detail and insight.

–Patricia Lee, PhD Student at UC Irvine (CS)

Read more about their take on the technical presentations on the Obsidian Blog.

Greg Smith, Sr. Verification Manager at Oracle

Abstract:
So much of today’s metrics used to gauge the progress of a verification project are backwards looking – telling us what ground we have covered. In addition, many metrics commonly in use are subjective and prone to human errors of omission.  I would like to present a different approach to DV project metrics using bug arrivals to actually provide some predictive capability as well as aid in overall project planning.

Download the Presentation Here
Download the “Sample Metrics” File Here

High Performance Collection of Coverage Metrics Using a Relational Database Backend

James Roberts, Sr. Verification Engineer at Oracle

Abstract:
A database is an ideal medium for collecting and analyzing coverage. At Oracle, we marry our Oracle database with coverage collection of our verification, and then use SQL to extract coverage metrics on-demand. This presentation outlines an intuitive scheme for database collection of coverage, and presents data showing the scalability and the high bandwidth this scheme is able to handle.

Download the Presentation Here

Verification Tutorial I – Stick a Fork in it: Applications for SystemVerilog Dynamic Processes

Focus: Verification and modeling
Audience: Verification engineers, but designers may find interesting
Skill level: Basic to Advanced Verilog/SystemVerilog

Description: In Verilog, processes come in the static form of always and initial blocks, concurrent assignments, and the fork..join statement. SystemVerilog introduces dynamic processes in the form of new fork..join statements and the std::process class. This presentation explores several applications for dynamic processes in verification and behavioral modeling such as how verification methodologies create independently executing components and control simulation phasing, isolating random number generators for test reproducibility, parallelizing testbench interaction with DPI code, and a way of using dynamic processes with SystemVerilog interfaces to create bus resolution functions and model analog behavior.

Verification Tutorial II – Getting Started with OVM (UVM)

Focus: Verification
Audience: Designers and verification engineers adopting or considering OVM (UVM)
Skill Level: Intermediate – recommended knowledge of class-based SystemVerilog

Description: Basic introduction to OVM. Simple environment presented showing the steps and code required to create an OVM (UVM) testbench environment.

Verification Tutorial III – Introduction to SystemVerilog Assertions (SVA)

Focus: Verification
Audience: Design and verification engineers
Skill Level: Basic – no SystemVerilog required, but some an HDL recommended

Description: Basic introduction to the SystemVerilog assertion language. Intended for those who have no knowledge of SVA and interested in what it’s all about.

Scope

The purpose of MTV is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa. This is the 11th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross-examination of test and verification experiences and innovative solutions.

Areas of Interest include

* Validation of microprocessors and SOCs
* Experiences on test and verification of high performance processors and SOCs
* Test/verification of multimedia processors and SOCs
* Performance testing
* High-level test generation for functional verification
* Emulation techniques
* Silicon debugging
* Formal techniques and their applications
* Verification coverage
* Test generation at the transistor level
* Equivalence checking of custom circuits at the transistor level
* ESL Methodology
* Virtual Platforms
* Software verification
* Circuit level verification
* Switch-level circuit modeling
* Timing verification techniques
* Path analysis for verification or test
* Design error models
* Design error diagnosis
* Design for testability or verifiability
* Optimizing SAT procedures for application to testing and formal verification

Advance Program

2010 Advance Program (PDF)

Registration

IEEE Online Registration Link: click here
If you are unable to use the above link please use this PDF

JOB POSTINGS UPDATED – OCT 29, 2010

The application deadline for the MTV Scholarship Program is now less than 30 days away. This scholarship will provide round-trip airfare, conference registration fees, and hotel accommodations for several students across the nation to attend the 11th annual workshop on Microprocessor Test and Verification in Austin, TX.

“It’s always difficult to have to choose applicants”, said Eric Hennenhoefer, President of Obsidian Software. “There are so many talented young engineers out there, and we like to help really determined and motivated individuals whenever we come across them.”

2010 marks the first year of this scholarship, which is open to applicants until October 1st. More information can be found by visiting the scholarship program page:

2010 Microprocessor Test and Verification Scholarship

The notoriety of DVClub is spreading organically by word of mouth – something that’s not easy to achieve among a community of engineers. “We continually see new people at each event” said DVClub founder and organizer Eric Hennenhoefer. “Once they’ve experienced a DVClub event, they tend to come back to future events and bring more co-workers with them”. The average quarterly growth rate for DVClub in 2010 has been around 7% per quarter and climbing.

About DVClub:

The principal goal of DVClub is to have fun while helping build the verification community through quarterly educational and networking events. Currently over 50 advisors actively keep the club organized by brainstorming on topics, tracking down speakers, promoting events, and helping out on event day.

Complexity

In his recent presentation discussing verification of the Power7 processor, John Ludden of IBM opened with a quote from an IBM exec more than a decade ago. “it’s not rocket science”- a perception held by some members of the management and design communities at that time.

However, designs have become a whole lot more complex over time. The Power7 processor at 45nm has 1.2B transistors on a 567 sq. mm die, supporting 8 cores with 4 threads each, an on-chip eDRAM, 3 levels of caches and 2 DDR memory controllers. Yet as verification complexity multiplies in this multi-threaded design, it’s very helpful to have some of the more advanced tools and methodology at your disposal.

Tools and Methodology

Fortunately for Ludden and the Power7 team, IBM has invested in verification technology for years (in spite the quote from the exec). The company continues to develop and rely on in-house tools for many of the advanced verification technologies for processor-specific testing. These include the test-bench, multi-thread test generators, hardware accelerators, formal and semi-formal tools, micro-architecture checkers (API based), cache coherency checkers and coverage tools. Exercisers
originally developed for post-silicon validation were used to exploit the hardware acceleration platform. Forty-five thousand coverage points were organized to assist with big picture and were used to re-direct the test generator and exercisers for accelerators.

To support corner case testing for events that occur rarely, especially in multi-threaded scenarios, software irritator threads were used. These irritators are capable of creating the worst possible contentions. Through their application, twenty-three high quality bugs were revealed hiding in the corners.

A methodical application of these tools and technology clearly captured and advanced the industry best practices.

Designing for Verification

Designing for Verification was an important element in managing the overall risk to verification time line. IBM minimized the risks by maintaining a tight interaction between the specification and verification teams during the design phase and allowing the verification team to maintain architectural changes. “Chicken switches” were placed in silicon that allowed verification team to back-off an area considered risky or possible of otherwise compromising the verification effort. These switches provide workarounds, with some small impact on performance but no functional change, for accessing difficult to verify micro architectural features. Hardware irritators were also used to enable stress testing of corner cases in both pre-silicon and post-silicon testing.

Conclusion

The Power7 draws many architectural features from the Power5 and 6 designs, although it is a much more complex and powerful processor with a much shorter verification cycle. Ludden and the Power7 team accomplished this remarkable feat with a lot of foresight in planning, metrics collection and careful execution. Tight interlocking between metrics collected and verification plan was key part of tracking mechanism and functional closure. This project should serve as an example of how to plan for and manage risks in a complex verification project.

Kudos to John and the IBM team. His full presentation can be downloaded here.

Normal Accidents : Living with High-Risk Technologies
Charles Perrow

A History of Murphy’s Law
Nick T. Spark

Inviting Disaster: Lessons From the Edge of Technology
James R. Chiles

Fluid Concepts And Creative Analogies: Computer Models Of The Fundamental Mechanisms Of Thought
Douglas R. Hofstadter

The Challenger Launch Decision: Risky Technology, Culture, and Deviance at NASA
Diane Vaughn