Tags
analog automation analog verification Architecture ASIC Brian Bailey Cadence checkers C model Complex Architectures corner cases coverage coverage driven methodology coverage grid Coverage metrics coverage monitors DAC Dave Whipp Debugging Design design entry designers' guide consulting digital verification directed assembly code tests directed testing Distribution of Coverage Points Doug Smith Doulos DVClub DVCon emulation Eric Hennenhoefer ESL formal verification functional design verification functional verification general purpose microprocessor modeling OVM RTL testbench SystemVerilog Technical Review UVM Validation Verification verification jobs
Author Archives: eric
Posted on November 14, 2008 by eric
Joseph Hupcey of Cadence reviews Dr. Henry Chang’s presentation on analog and mixed signal verification. Continue reading →
Posted in Technical Review
|
Tagged analog automation, analog verification, Cadence, design entry, designers' guide consulting, digital verification, Henry Chang, interface errors, Joseph Hupcey, RTL verification, schematic capture
|
Comments Off
Posted on October 2, 2008 by eric
Eric reviews John Ludden’s verification strategy for IBM’s POWER6 architecture and discusses the complexity of verifying a modern in-order processor. Continue reading →
Posted in Technical Review
|
Tagged High Frequency, IBM, In Order, infinite state, John Ludden, MP/SMT, MT, Out of Order, POWER5, POWER6, RAS, Simultaneous Multi Threading, SMT, Software Simulation, Verification
|
Comments Off
