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analog automation analog verification Architecture ASIC Brian Bailey Cadence checkers C model Complex Architectures corner cases coverage coverage driven methodology coverage grid Coverage metrics coverage monitors DAC Dave Whipp Debugging Design design entry designers' guide consulting digital verification directed assembly code tests directed testing Distribution of Coverage Points Doug Smith Doulos DVClub DVCon emulation Eric Hennenhoefer ESL formal verification functional design verification functional verification general purpose microprocessor modeling OVM RTL testbench SystemVerilog Technical Review UVM Validation Verification verification jobs
Author Archives: admin
Posted on March 27, 2009 by admin
This article presents an overview of functional design verification using a coverage driven methodology while attempting to answer the question of how much testing is enough. Continue reading →
Posted in Technical Review
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Tagged checkers, Complex Architectures, corner cases, coverage driven methodology, coverage grid, Coverage metrics, coverage monitors, directed assembly code tests, directed testing, Distribution of Coverage Points, functional design verification, general purpose microprocessor, mobile computing, random test generator, RTL testbench, Verification Progress
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Posted on March 23, 2009 by admin
By Grant Martin This blog post originally appeared at: http://www.chipdesignmag.com/martins/2009/03/19/bailey-on-verification-at-the-club/ — March 19, 2009 @ 11:14 pm Today I attended the latest meeting of the Silicon Valley branch of the DVClub. For those not familiar with the DVClub (DV = … Continue reading →
Posted in Silicon Valley, Technical Review
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Tagged Brian Bailey, DVClub, Eric Hennenhoefer, Is it time to declare a verification war?, Silicon Valley, Technical Review
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Posted on February 27, 2009 by admin
There is a vast landscape of test generators used in the industry today. These range from simple scripts and parameterized macros that can be created in a matter of weeks to full featured systems used by cutting edge processor verification … Continue reading →
Posted on February 20, 2009 by admin
Anyone who has worked on a microprocessor design in recent years knows that verification has become a larger and larger share of the effort to bring a product to market. Designs are becoming increasingly complex and this complexity is often … Continue reading →
Posted in Technical Review
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Tagged emulation, hardware based verification, RTL emulator hybrid, RTL testbench, verification completion, verification platforms
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Posted on August 28, 2008 by admin
This blog explores the theories of NVIDIA’s Dave Whipp on restructuring DV workflow by using C models in place of the natural language specification. Continue reading →
Posted in Technical Review
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Tagged Architecture, ASIC, C model, checkers, Dave Whipp, Debugging, Design, ESL, Methodology, NVIDIA, Spec, testbench, Validation, Verification
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