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Presenter:

Tim Stremcha, Sr. Design Engineer at Open-Silicon Inc.
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This discussion will examine the trajectory of Formal Verification (FV) by reviewing one user's experiences under various use models across approximately 15 years.  Past and present challenges to wider deployment of FV within design and verification groups will be explored, as well as a reflection on realized benefits, and future expectations

Bio:

Tim Stremcha has more than 20 years of experience designing leading edge IC's and systems. He began his career in the high performance computing (HPC) realm at Cray Research and SGI. Since then he has worked for a design services enterprise that has served a broad range of market segments focused on aggressive design challenges.