Upcoming Events

Overview:
This presentation and talk will present the two major approaches to ESL design entry and what is expected of the designer in each case. A specific coding example will be presented illustrating what is expecting too much of a C to RTL compiler, (and thus gets both the designer and the tool into trouble), plus the coding required to remedy the problem.

Speaker:
Chad Spackman, Verification Technologist

Abstract:
The capabilities and promise of advanced software-like HDL has been in the works for many years. There are now big players in the arena. But who uses these tools, and are there successes? It would seem ESL only has a cult following. There exists a majority of designers out there who believe ESL cannot deliver the control and quality of results that traditional HDL approaches allow. The fact of the matter is that some of these tools can indeed produce high quality results in a drastically reduced time frame. However, ESL acceptance is hampered by lack of knowledge of what they do and how design entry must change in order to achieve acceptable results. They are also substantially hampered by what amounts to outlandish promises by those trying to pedal the tools, touting capabilities that have not yet been achieved. The end result is disappointment.

Bio:
Chad Spackman, founder and CTO of two ESL based IP companies, has 20 years of semiconductor design experience and holds five patents in the field. Chad's achievements include over a dozen analog designs for various foundries, six large-scale communications ASIC designs in the communications sector, and a complete TCP/IP TOE engine licensed to a major semiconductor company. Chad holds a BA in physics and Bachelor and Master's degrees in Electrical Engineering from the University of Pennsylvania and Penn State University, respectively.

Presentation Notes:
PDF slides