Upcoming Events

The location for the Analog Mixed-Signal verification event on Monday the 6th of December will be ST-Ericsson Eindhoven, HTC 41, 2nd floor, meeting room 205 (left after exiting the elevator). Please let Dennis Knijnenburg know that you will attend this event, so he can register you at the reception of HTC41.

Register Here for this Event

Presentations:

“Advanced methodologies used for top-level verification of mixed signal products”, Roger Witlox, Sr. Verification Engineer, PL Integrated IVN & FlexRay, NXP
PDF Slides

The described verification approach is used to verify IC’s that are used in automotive in-vehicle networks. Examples are LIN, CAN and Flexray transceivers. Transceivers are mixed signal designs that translate a digital signal into an analog signal and vice versa and are used in the physical layer of a network. Due to trends like power modes, digital trimming, auto calibration and integration these mixed signal designs are becoming more and more complex. As a result a commonly used architecture contains a central digital state-machine that controls the surrounding analog modules. This all requires a more advanced overall verification approach.

One of the instruments used in this overall verification approach is top-level (chip-level) verification. The goal of top-level verification is to prove interconnect and interoperability. It assumes that functionality is verified at IP-level. The types of bugs hunted with this approach include: wrong polarity, flipped busses and chicken & egg problems. Top-level is always subject to late design changes and often timing critical towards tape-out, therefore the following methods are used: Self-checking, Modeling, Reusability and Functional coverage.


“Analogue Behavioural Modelling: An Inconvenient Truth”, Dave Wiltshire, Texas Instruments, UK
PDF Slides

The complexity of SERDES designs has resulted over several years in increased analogue complexity. This extra complexity means that simple behavioural models cannot be used to test everything in a design. This presentation will discuss the different strategies that have been developed with the TI SERDES design team solve the problem of verifying a complex mixed signal design using Verilog simulators. The following development strategies will be used.
Using standard digital verilog simulation:

• Model analogue behaviour using verilog reals
• Solving how to pass verilog reals across module boundaries
• Migrating to VerilogA behavioural models
• Verifying that the models match the transistor implementation
• Solving the simulation speed issues (wreal)

“Using assertions in AMS verification”, Scott Little, AMS Verification Engineer, Freescale
PDF Slides

Assertions have been used successfully in digital verification methodologies for a number of years. As the size and complexity of AMS blocks and SoC designs increase, there is an increasing need for assertions capable of specifying and checking AMS behaviors. We discuss ongoing work within Freescale and the Accellera AMS Assertions sub-committee to develop, standardize, and deploy AMS assertions.