Upcoming Events
Event
- Title:
- Bristol - Mainline Functional Verification of IBM's POWER7 Processor Core
- When:
- 11.01.2010 11.30 h - 14.00 h
- Where:
- Bristol
- Category:
- Bristol
Description
At various locations
- Bristol: Infineon, Great Western Court, Hunts Ground Road, Stoke Gifford, BS34 8HP
- Cambridge: The ARM office in Cambridge (110 Fulbourn Road, Cambridge, CB1 9NJ, England)
- Remote Access: Access from your desktop (details to follow)
- Eindhoven: Details to follow
Agenda:
| 11.30 | Networking, drinks and buffet |
| 12.00 | Introduction, Mike Bartley, TVS |
| 12.05 | “Mainline Functional Verification of IBM's POWER7 Processor Core”, John Ludden, Senior Technical Staff Member with IBM's Systems and Technology Group IBM's POWER7 processor chip officially began shipping in IBM's POWER Systems servers in early 2010. The Power 750 Server is the industry's highest performing 4-socket system. The POWER7 chip contains 8 processor cores, each capable of executing up to 4 threads simultaneously. This presentation will give an overview of the verification methodology for the POWER7 processor core mainline function. This methodology led to outstanding first-pass hardware quality. There will be a brief introduction to the POWER7 chip and core microarchitecture followed by detailed discussions of Simultaneous Multi-Threading (SMT) verification, test plan development, coverage methodology and a look at IBM's simulation acceleration platform usage. John Ludden is a Senior Technical Staff Member with IBM's Systems and Technology Group. He joined IBM in 1990 after receiving a B.S. degree in Electrical Engineering from the Rochester Institute of Technology in Rochester, NY. His work at IBM has spanned mainframes systems, x86 processors and Unix servers. Mr. Ludden has served as the architecture verification lead engineer for the POWER3 through POWER7 processor products. He has worked with the IBM Haifa Research Laboratory in Israel for 17 years to advance the primary instruction level test generation tools used to verify all current processors within IBM. He holds several patents, has published multiple papers in the field of processor verification and pioneered the simultaneous multi-threading verification methodologies currently employed by IBM. Following a 4-year assignment in Austin, TX, John relocated back to IBM's Burlington, VT facility where has worked remotely for the POWER processor development team based in Austin for the past 10 years. |
| 13.00 | Q&A |
| 13.30 | Networking, drinks and buffet |
| 14.00 | Finish |
Don’t miss out – register now for this free event at http://dvclubbristol.eventbrite.com or get more details by emailing Mike Bartley.
This event is sponsored by ARM, Infineon, the NMI and TVS
Venue
- Venue:
- At Various Locations
- Street:
- Great Western Court, Hunts Ground Road, Stoke Giff
- ZIP:
- BS34 8HP
- City:
- Bristol
- Country:
- UK
