Upcoming Events

Event

10:30-11am	Coffee/Snacks
10:45-11:00am	Introduction to DV Club, welcome the gathering followed by first Speaker introduction - Rajiv Nadig
11-11:30am	"Verification strategy that enabled deployment of PCI-express GEN 1 devices – focus on compliance/performance/functional verification" by Pradip Thaker, Analog Devices, Bangalore
11:30-11:35am	Speaker introduction - Robin George
11:35-12:05pm	"Nanometer Testing: Challenges and Solutions" by Jais Abraham, MTS, AMD, Bangalore
12:15-1:00pm	Lunch/interaction

Dr. Pradip Thaker - Analog Devices, Inc. Bangalore
Verification Strategy for PCI Express - ppt (220K)

Dr. Pradip Thaker has 15 years of industry experience combined both as a technical manager and as an individual contributor in developing large and complex ICs for networking, multi-media and computer connectivity with semiconductor and system companies in USA and India.
He also served as an adjunct faculty at the George Washington University (Washington DC, USA) from years 1993-2003 where he designed and taught undergraduate and graduate level VLSI courses on part-time basis. He received BE (ECE), MS (EE) and PhD (VLSI Systems) in 1989, 1993 and 2000 respectively. He is currently with DSP IC Division of Analog Devices, Inc. in Bangalore, India.
Dr. Pradip Thaker is the recipient of industry and academic awards for excellence. He has published in international conferences and regularly reviews papers for the same. His technical contributions in industry are in the areas of architecture definition, RTL implementation, verification, synthesis and DFT. His academic research interests are in area of DFT and verification.

Jais Abraham - AMD Design Centre Bangalore
Nanometer Testing: Challenges and Soultions - ppt (2.2M)

Jais Abraham graduated from the Indian Institute of Technology at Chennai, India. He has over 10 years of experience in the area of VLSI Design-For-Test, working at Texas Instruments (India), InnoDes Solutions and Montalvo Systems. Currently, he is a Member of Technical Staff at the AMD India Design Centre, Bangalore.
During the span of his career, he has been involved in defining the DFT features of complex designs ranging from high speed processors to multi-million gate SOCs on cutting edge technologies. He has co-authored several papers in National and International conferences and holds 6 patents in the area of DFT.