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The Cortex-A15 Verification Story

Learn the details of verifying the Cortex-A15 MPCore: this processor has an out-of-order superscalar pipeline with a tightly-coupled low-latency level-2 cache which can be up to 4MB in size. It can be configured in clusters with up to 4 cores, and supports MP cache coherency in hardware.  Additional improvements in floating point and NEON™ media performance result in devices that deliver the next-generation user experience for consumers as well as high-performance computation for web infrastructure applications. This processor introduces new technology that enables efficient handling of complex software environments including full hardware virtualization, Large Physical Address Extensions (LPAE) addressing up to 1TB of memory as well as error correction capability for fault-tolerance and soft-fault recovery.

Abstract:

This presentation will describe the advanced verification methodologies which are employed in the verification of Cortex-A15, including:

• Constrained random SystemVerilog unit level testbenches
• Coverage driven methodology utilizing black box and white box functional coverage for each unit
• Assertion based design where assertions are added by both verification engineers as well as RTL designers
• Top level (full CPU cluster) verification with multiple diverse random instruction generators, focusing on comprehensive ISA coverage and extensive stress of MP cache coherency
• System level (multiple CPU clusters + interconnect, memory controllers, graphics accelerators, other peripherals) emulation of the platform to enable booting of operating systems and running stress testing applications and workloads
• FPGA platforms to provide additional cost effective throughput

Speaker Bio:

Bill Greene, Austin CPU Validation Manager, ARM, is the engineering manager for the CPU Validation Team at ARM in Austin.  He previously worked at Intel on Itanium processor validation and firmware development, and as RTL and verification manager at Marvell developing ARM-based SoCs for mobile applications.  He holds BSEE/BSCE and MSEE degrees from Purdue University.
Micah McDaniel, Principal Design Engineer, ARM, was the verification lead for the Cortex-A15 processor.  At ARM he was previously an RTL designer and verification engineer on Cortex-A8.  He has also done RTL design at Chicory Systems, and circuit design at IBM.  He holds an MSEE from the University of Texas, and BSEE/BSCE and BSPHYS from Louisiana State University.