Upcoming Events
Event
- Title:
- Austin - Q4 2009 -Verification of the CoreNet Fabric with SystemVerilog
- When:
- 12.09.2009 11.00 h
- Where:
- Cool River Cafe - Austin, TX
- Category:
- Austin
Description
Speaker:
Sakar Jain, Freescale Semiconductor - Networking and Multimedia Group
Sakar Jain is a Senior Verification Engineer in Networking and Multimedia Group (NMG) at Freescale Semiconductor, Austin Texas. He has many years of progressive experience in using advanced verification methodologies for design verification of microprocessors and SoCs. He is currently working on QorIQ line of communication processors from Freescale. Prior to joining Freescale, Sakar worked at IBM, Austin and was a key member of Cell microprocessor design team.
Abstract:
The advanced Freescale QorIQ communication platform containing CoreNet fabric enables the next era of
networking by offering advanced levels of performance, power-efficiency and programmability.
Read the full description.
Presentation Notes:
PDF Slides
Agenda:
11:00am - 12:00pm ............ Networking, Social hour
12:00pm-1:00pm ................ Formal Introduction of Speaker, Lunch Served during Presentation
1:00pm -2:30pm ................. DVClub University: Insightful Presentations by our Sponsors – approx 25 min each
DVClub University Speakers:
- Ashwin Matta, Denali - Verification Plannng for Complex Protocols
- Doug Smith, Doulos - How to Handle Asynchronous Behaviors Using SVA
- Dmitri Pavlovsky, Cadence - Tackling difficult corner case scenarios in PCI Express verification using a Metric Driven Approach
Venue

- Venue:
- Cool River Cafe - Website
- Street:
- 4001 Parmer Lane
- ZIP:
- 78727
- City:
- Austin, TX
- Country:
-
