Upcoming Events

Hands-On Verification

Doug Smith, Engineer/Instructor, Doulos

A Two Part Talk on UVM, the Universal Verification Methodology, for Functional Verification

Part One: Easier UVM - Functional Verification for Mainstream Designers

Easier UVM is an approach to using Accellera's UVM, the Universal Verification Methodology, for functional verification by mainstream hardware designers as opposed to power users with verification specialist skills. Easier UVM arises from experience at Doulos in teaching SystemVerilog and functional verification methodology to engineers from a broad cross-section of the hardware design and verification community.

Part Two: UVM Register Abstraction Layer

The UVM Register Abstraction Layer has been generating a lot of industry interest lately. In this phase of the talk, aimed at power users, Doug Smith will cover the necessary templates to develop a UVM environment as well as discuss how to model a register map, an essential part of any verification environment.