Jacob A. Abraham - University of Texas at Austin

Practical Formal - Mainstream Formal for the Rest of Us - pdf

• Austin - Q1 2007
• Jacob A. Abraham is a Professor in the Department of Electrical and Computer Engineering at the University of Texas at Austin. He is also director of the Computer Engineering Research Center and holds a Cockrell Family Regents Chair in Engineering. He received the Bachelor's degree in Electrical Engineering from the University of Kerala, India, in 1970. His M.S. degree, in Electrical Engineering, and Ph.D., in Electrical Engineering and Computer Science, were received from Stanford University, Stanford, California, in 1971 and 1974, respectively. From 1975 to 1988 he was on the faculty of the University of Illinois, Urbana, Illinois.
• Professor Abraham's research interests include VLSI design and test, formal verification, and fault-tolerant computing. He is the principal investigator of several contracts and grants in these areas, and a consultant to industry and government on testing and fault-tolerant computing. He has over 300 publications, and has been included in a list of the most cited researchers in the world. He has supervised more than 60 Ph.D. dissertations. He is particularly proud of the accomplishments of his students, many of whom occupy senior positions in academia and industry. He has served as associate editor of several IEEE Transactions, and as chair of the IEEE Computer Society Technical Committee on Fault-Tolerant Computing. He has been elected Fellow of the IEEE as well as Fellow of the ACM, and has been named as the recipient of the 2005 IEEE Emanuel R. Piore Award.

Chuck Alley - IBM

Using PSL and FoCs for Functional Coverage Verification - pdf

• RTP - Q1 2007
• Chuck Alley is an Advisory Engineer at IBM, in the IBM Systems and Technology Group. He has spent the last 11 years with IBM, specializing in microprocessor development, and functional verification of microprocessors and microprocessor systems in particular. Currently, he is working on verifying the L2 cache subsystem for a large scale-out processor design. In the past he has worked on most of IBM's embedded CPU offerings, two of their three game systems, and two of their most recent server processors. Chuck has written and delivered papers at the IEEE CICC (custom integrated circuits conference) in San Jose and at IBM's Verification Conference in Germany and Poughkeepsie, NY. He has two verification related patents (applied for and pending).
• Although Chuck spends most of his time working, he does manage to make time for his favorite television shows. To distinguish himself from the great masses of engineers surrounding him, he plans on investing his free time in ventures around the North Carolina area, such as week-long backpacking trips in the Great Smoky Mountains. To date, however, he has not had the time.

Edward Arthur - Cisco Systems

Accelerated System DV Through Reuse - pdf

• Boston - Q2 2007
• Edward is a Hardware Engineer for Cisco Systems in Boxborough, MA performing ASIC, FPGA and system-level verification for cable modem termination systems, service provider routers and network processors. He has been at Cisco for over five years, before that working at two successful startups and a number of Fortune 500 companies. After 20+ years in industry and two EE degrees he has managed to stay firmly entrenched in a cube.

Rekha Bangalore - Freescale Semiconductor

Formal Verification Techniques - pdf

• Austin - Q1 2007
• Rekha K. Bangalore ( This e-mail address is being protected from spambots. You need JavaScript enabled to view it ) is a functional verification manager in the wireless division of Freescale Semiconductor Ltd. The focus of the group is on System on Chip and System Verification and keeping up with the industry verification methodology. Rekha is responsible for defining the strategy for pre-silicon verification and implementing it with the team to ensure quality silicon to customers with zero defects. With integration of external IP's and complex architecture, functional verification is becoming challenging and is one of the key initiatives.
• Prior to Freescale, Rekha worked in Motorola and Intel Corporation, Chandler AZ. Rekha's experience is very diverse and includes architecture, system validation, Design for Test, and Functional Verification. Rekha has several patents that have been approved for filing and has also published technical papers in EDA user's conference and IEEE conferences. She also holds a BE in Electronics Engineering from Bangalore, University India and a MS in Computer Engineering in the United States.

Jason Baumgartner - IBM

Integrating Formal into Main-Stream Verification: The IBM Experience - pdf

• Austin - Q1 2007
• Jason Baumgartner joined the IBM Server Group in 1995. He is the technical lead of the SixthSense project, which is a toolset for formal and semi-formal functional verification, and sequential equivalence checking. He received his PhD from the University of Texas at Austin in 2002.

Raj Dayal - Qualcomm

Managing Deployment of SVAs in Your Project - pdf

• RTP - Q2 2007
• Raj is currently working for Qualcomm Corp. Processor Solutions Group in Cary, NC where he is responsible for Processor Verification, tools and Methodologies development.
• Prior to joining Qualcomm, Raj held a number of Design and Verification Team Lead positions at Ivivity (Storage Processor startup in Atlanta), Verification Manager. Vitesse Semiconductor ? (Internet Traffic Management QoS - startup Orologic) Verification Lead. Broadband Technologies ? (Fiber to Curb SONET Framer), Lead Design Engineer Avant! (now Synopsys) ? CAD Tools Developer. IBM PC Company in RTP Area ? Device Driver Development. Raj worked as an ASIC Design Engineer in IBM Interconnect Division in Mid Hudson Valley, upstate New York. Raj has lectured a few courses in C Programming and LAN in Wake County Community College. Raj received his MSEE from Syracuse University and BSEE from NJ Institute of Technology.

Ish Dham - Texas Instruments

Design Verification to Application Validation of a Multiprocessor SoC - pdf

• Bangalore - Q4 2007
• Ish Dham did his B.Tech in Computer Science from IIT, Chennai in 1996 and has been with Texas Instruments since. Ish Dham has worked on simulation models for instruction set simulation, Architecture exploration and as reference models for design verification. He currently leads the design verification activities in the DSP System Design Group in TI India where he has been using formal and simulation based methods to verify complex DSP IPs and SoCs.

Sadik Ezer - Diamond Video Products, Tensilica Inc.

• Silicon Valley - Q4 2007
• Sadik Ezer is the Lead Verification Engineer of Diamond Video products at Tensilica Inc. He has been with Tensilica for six years. Before that he worked in SGI (Silicon Graphics Inc.), Mountain View for four years as Senior Verification Engineer, and in Managed Information Technology Systems (MITS) in Sydney, Australia, as Software Engineer for two years. He received his Bachelor's and Master's degrees (on DSP and Image Processing) in E.E. from Bogazici University, Istanbul, Turkey, in 1990 and 1992. He has three conference papers, the last one was presented at DAC 2005, titled Smart Diagnostics for Configurable Processor Verification.

Bill Flederbach - Qualcomm

• RTP - Q2 2007
• Senior Director of Engineering, Qualcomm RTP

Mark A Firstenberg - IBM

Experience with Formal Methods, Especially Sequential Equivalence Checking - pdf

• Boston - Q1 2007
• The relationship between formal and simulation based verification methods, as well as when and where they are applicable, will be discussed. Semi-formal methods, boolean equivalence checking and sequential equivalence checking will be defined. The application of sequential equivalence checking on two projects will be detailed, including lessons learned.
• Mark Firstenberg joined IBM's Systems and Technology Group in July 2004 as a Senior Technical Staff Member. He has been developing and deploying a flow which systematically uses sequential equivalence checking across an entire project. Previously, Mark served as the RTL methodologist for Sun's UltraSPARC V processor, supported design verification tools and flows at Stratus Computer and investigated hardware/software co-design at Viewlogic Systems. At Digital Equipment Corporation, Mark wrote two cycle-based simulators, served as a logic designer for the VAX 9000 (receiving four patents) and wrote microcode for the VAX 8800. Mark holds a BSEE from Cornell University.

Angela Hopkins - Ericsson Mobile Platforms

Constrained-Random Verification Strategies in Ericsson - pdf

• RTP - Q3 2007
• Angela Hopkins is a Senior Staff Engineer at Ericsson, Inc in the Digital Baseband ASIC Design team. She has architected and developed constrained-random Verification Environments for block and subsystem CPU peripheral designs. Her efforts have driven delivery of high quality IP for SoC integration. She has previously held design and verification positions at Digital Equipment Corporation and Mitsubishi Electronics. She joined Ericsson in 2004 and received her BS degree in electrical engineering from Howard University.

Anoosh Hosseini - Cisco Systems

Simulation versus Acceleration versus Emulation - pdf

• Silicon Valley - Q2 2007
• Anoosh has over 20 years of industry experience at Intel, Mips, SGI, Sun, Equator Technologies, Stratumone, and Cisco Systems. Projects included microprocessor verification, design verification tools, system simulation, distributed simulation, C modeling, fast instruction set simulators, and IDE development.
• Current interests are advanced embedded software development tools. Most recent projects include C modeling and system simulation for Cisco's flagship CRS-1, and modeling & IDE development for Cisco's next generation packet processor. Anoosh has a BSEE from Virginia Tech and a MSCE from Santa Clara University.

Asad Khan - Texas Instruments

• Dallas - Q1 2007
• Asad Khan, design verification lead for the Connectivity Interface Solutions Group in High Performance Analog at Texas Instruments, holds a BSEE (summa cum laude) from University of Texas at Arlington, and an MSSE from Southern Methodist University, Dallas, Texas.
• Asad specializes in ground-up development of verification architectures with focus towards coverage-driven verification, efficient self-checking reference modeling techniques, definition of verification methodologies, and mixed signal verification. Asad has worked on the verification of multiple products based on USB 3.0, USB 2.0, PCI Express, 1394, PCI, technologies, and SERDES/PHY while at Texas Instruments.

Jai Kumar - Sun Microsystems

HW Emulators: Does it Belong in your Verification Toolchest? - pdf

• Silicon Valley - Q2 2007
• As a Verification Technologist in Systems Group within Sun Microsystems, Jai spearheads the evaluation and deployment of state-of-art verification tools, technologies and methodologies to enhance functional verification efficiency for large-scale, complex processor designs at Sun.
• Jai was instrumental in successful deployments of several acceleration technologies leading to high impact on UltraSPARC verification at Sun. Jai also has extensive management, technical experience in successful injection of simulation, emulation and formal technologies on over 20 design projects during his career at Motorola and Fujitsu. An active contributor to the industry, Jai plays active role in the industry, has chaired conferences, and has authored numerous publications and received awards in the areas of Simulation, Emulation and Formal Verification. to his credit.

Grant Martin - Tensilica, Inc.

• Silicon Valley - Q4 2007
• Grant is currently a Chief Scientist at Tensilica, Inc. in Santa ClaraBefore that, Grant worked for Burroughs in Scotland for six years; Nortel/BNR in Canada for 10 years; and Cadence Design Systems for nine years, eventually becoming a Cadence Fellow in their Labs. He received his Bachelor's and Master's degrees in Mathematics (Combinatorics and Optimisation) from the University of Waterloo, Canada, in 1977 and 1978.
• Grant is a co-author or co-editor of nine books dealing with SoC design, SystemC, UML, modelling, EDA for integrated circuits and system-level design, including the first book on SoC design published in Russian. His most recent book, ESL Design and Verification, written with Brian Bailey and Andrew Piziali, was published by Elsevier Morgan Kaufmann in February, 2007.
• He was co-chair of the DAC Technical Programme Committee for Methods for 2005 and 2006. His particular areas of interest include system-level design, IP-based design of system-on-chip, platform-based design, and embedded software. Grant is a Senior Member of the IEEE.

Dina McKinney - AMD Design Center

• Austin - Q2 2007
• I've worked in microprocessor design in various roles my entire career, all 24 years. Microprocessor design has all the characteristics of a great adventure. There is excitement, creativity, passion, drive, determination, surprise, success and tremendous challenge. You learn to love the journey, count on your team, and eagerly anticipate the joy of success, achieving the goal, leaving your mark, moving others forward.
  
  At the North Austin Design Center, we?re always trying to find new ways to leap forward, innovate, outsmart, outguess. Most folks in Austin don?t realize AMD has a microprocessor design site located in the Arboretum. It?s our stealth move?come check us out.

Robert Metzger - Hewlett-Packard

• Dallas - Q1 2007
• Debugging is primarily an analytic activity, in contrast to the other phases of the software development cycle, which are primarily constructive. Software developers can benefit from using the analytic methods of a variety of other intellectual disciplines. These disciplines each have a point of analogy with debugging, a set of assumptions that form a worldview, and a set of techniques. This talk will briefly explore debugging techniques derived from the following intellectual disciplines:
  
  - fictional detectives seeking criminals
  - mathematicians constructing proofs
  - safety experts investigating accidents
  
  These techniques will be presented in the 'patterns' paradigm widely employed in recent software engineering literature. Visit the Debugging by Thinking website for more information on this topic.
• Robert Metzger is currently a senior software engineer at Hewlett-Packard in Richardson. He has worked as a programmer developing financial applications, optimizing compilers, programming tools, system administration tools, and graphical user interfaces using a wide variety of programming languages and operating systems. He has managed programmers developing financial applications, optimizing compilers, and programming tools at three different companies.
• He is the author of "Debugging by Thinking: A Multi-disciplinary Approach", published by HP/Digital Press in 2004, and co-author of "Automatic Algorithm Recognition and Replacement", published by MIT Press in 2000.

Mike Mintz - Trusster

OOP for Hardware Verification - Demystified! - ppt

• Boston - Q2 2007
• OOP has become a mix of buzzwords, keywords, scare tactics, and techniques. This talk will cut through the jargon and present what OOP is and how to use it for verification. The talk will present a few basic, yet powerful OOP techniques suitable for large verification efforts.
• Mike Mintz of has been verifying for almost 10 years and has been programming in C++ for almost 20 years. He is co-author of "Hardware Verification with C++" and the new "Hardware Verification with SystemVerilog" books.

Scott Morrison - Texas Instruments

PCI Express Verification Using Reference Modeling - pdf

• Dallas - Q1 2007
• Scott Morrison is a Design Verification Engineer for Mixed Signal IP Development at Texas Instruments. Verifying high-speed mixed signal SERDES as well as catalog products such as PCI Express Switch, Scott has specialized in advanced verification methodologies including constrained-random stimulus with self-checking environments and coverage-driven verification. In 2003, Scott received his Masters of Engineering at the University of Florida, USA, specializing in Digital Hardware and Signal Processing.
• Reference modeling techniques for efficient verification of PCI Express Switch:
  With growing complexity of new PCI Express designs where opportunity for IP-reuse may be limited or none, achieving high-quality first silicon demands deployment of novel verification techniques. PCI Express switch incorporates complexities of packet switching with challenges of current and legacy specifications. One strategy in achieving high-quality PCI Express switch silicon is creating reference models or predictors that work in cycle accurate, packet accurate, or hybrid fashion to verify the design. This paper discusses techniques using Specman to create reference models for block-level testing in such a way that these models seamlessly integrate at the chip-level without additional effort.

Sunil Nanda - nVidia

Starting a VLSI Design Center in India - pdf

• Bangalore - Q4 2007
• Sunil Nanda did his B.E. in Electronics from BITS, Pilani, 1980 and followed it with a Masters in Electrical and Computer Engineering from University of Iowa, 1982. In his 25 years of industry experience, Sunil Nanda has worked for companies like Intel, Sun, Cadence, and S3. Projects he has worked on is similar to "who is who" - his contributions include graphics processor for P6 project, FP processor for SPARC, architect and lead designer for Integer and MMU for SuperSPARC (first superscalar), architected multiple innovative and ground breaking concepts for fast simulation, architected a dataflow scheduler, simulator and code generation system for DSP systems.
• Sunil established a design center for S3 in Bangalore from Ground Zero which worked on new design methodologies for multi-million gate designs for S3. Then he co-founded Thinkit Technologies Inc., built a crack engineering team in Bangalore, and team executed a number of projects in Ethernet switching domain for Level 1 and Acclaim. Thinkit got acquired by Intel in Feb 2000 - the first company acquired by Intel in South Asia!! After acquisition, Sunil continued as Co-General Manager for the Ethernet switching group at Intel for 2 years before he moved on to setup an ASIC design center in Bangalore for nVidia from scratch!! Within 3 years, Bangalore center has grown to 220 engineers with the capacity to engage in 3 simultaneous designs and one of the few handful design houses in India who cover the entire spectrum of ASIC design from architecture, RTL, verification, synthesis, timing, emulation, and silicon bring-up & characterization. nForce680i chipset which won about 100 awards worldwide was designed completely out of Bangalore!! Along the way, Sunil also filed patents and currently owns 7.

Joe Rash, VP of Business Development - CebaTech

Verification Planning and Metrics to Ensure Efficient Program Execution - pdf

• RTP - Q1 2007
• Joe has over 20 years of experience with developing and bringing to market complex semiconductor and software products that address the needs of the data communications and enterprise storage market segments. Most recently, Joe was the Senior Business Development Executive for Qimonda Corporation’s Networking and Storage Memory product line where he helped launch a new product line focused on meeting the specific needs of the networking and storage industries. Joe began his career at IBM Corporation where he developed ASICs and firmware for communication co-processor adapter cards and ATM switches and routers. He has held the position of Design Manager at Nortel Networks and Director of Engineering at Applied Micro Circuits Corporation. Joe is the co-author of seven chip design and data networking patents and serves on the Industry Advisory Board of North Carolina State University's College of Electrical and Computer Engineering.

Scott Runner - Qualcomm

Verification of Wireless SoCs: No Longer in the Dark Ages - pdf

• Silicon Valley - Q3 2007
• Scott Runner is currently the Senior Director of Design Verification (DV) for Qualcomm Inc. in San Diego where he helped found Qualcomm's verification organization.
• He has worked in engineering in the semiconductor and EDA industries for 24 years, holding positions as design Director at Conexant Systems Inc., founding member of DesignWare at Synopsys, and was a DSP and ASIC design engineer and manager of at Fujitsu Microelectronics. He has taped out over 44 chips and has authored over 22 papers & articles. He holds degrees in Physics and Computer Science from Georgia Tech (go Jackets :-)).

Geoff Shippee - Qualcomm

• Silicon Valley - Q3 2007
• Geoffrey Shippee currently holds the title of VP, Engineering at Qualcomm Inc. He is currently responsible for Qualcomm's WLAN product development group, formally Airgo. The WLAN product group was recently acquired by Qualcomm. Geoffrey has recently relocated from San Diego to the Bay Area to assume the WLAN position.
• Prior to relocating to the Bay Area, Geoffrey's responsibilities at Qualcomm included all MSM7k chip development, wired connectivity hw development activities, Qualcomm's DFT methodology and several advanced R&D product development activities. In this role, he was instrumental in re-defining several key hw development methodologies used by Qualcomm for it's chip development. Prior to this, Geoffrey spearheaded the foundation Qualcomm's GSM modem development effort. As a follow on to this, he ultimately took on responsibility for all Qualcomm's UMTS HW development.
• Geoffrey's experiences at Qualcomm have exposed him to a wide range of product development including: Infrastructure (Wired networking side as well as the wireless side), Globalstar (a satellite based communication system), Bluetooth, GSM, UMTS, 1x, and now most recently WLAN. In addition to these compelling wireless communication systems, he has also had to work on solving complex integration problem related to low power multi-media technologies.
• Geoffrey started his career with Qualcomm Inc in 1994, having graduated from Cal Poly, SLO with an MSEE.

Pradeep Sindhu - Juniper Networks

• Silicon Valley - Q1 2007
• Pradeep Sindhu founded Juniper Networks in February 1996 and has held several central roles in shaping the company, currently serving as Vice Chairman of the Board and CTO, where he is responsible for the company's technical roadmap as well as day-to-day design and development of future products. He served as Chairman and CEO for eight months when he founded the company and played a central role in the architecture, design, and development of the M40 router. Prior to Juniper Networks, Sindhu worked as a Principal Scientist and Distinguished Engineer at the Computer Science Lab at Xerox's Palo Alto Research Center (PARC), where he worked on design tools for VLSI and high-speed interconnects for shared-memory multiprocessors. His key roles in the architecture, design, and development of these machines led to the commercial development of Sun Microsystems' first high-performance multiprocessor system family, which included the SS1000 and SS2000. He holds a bachelor's degree in Electrical Engineering from the Indian Institute of Technology in Kanpur, as well as a master's degree in the same discipline from the University of Hawaii. In addition, Sindhu holds both a master's and doctorate degree in Computer Science from Carnegie-Mellon University.

Don Steiss - Cisco

• Dallas - Q2 2007
• Design verification on embedded processors is a difficult problem that has traditionally relied on a small number of high-quality hand-generated tests augmented by a large number of directed random tests. The directed random tests are usually of lower coverage quality than the hand-generated tests.
• This paper describes a layered self-checking test generation approach that allows for manual or automatic specification of coverage events on top of software layers that transform the processor state to the desired state for the next coverage event without manual code generation. The resulting tests have known coverage with the productivity of directed random tests.
• The test generator is built in four layers: a test specification layer, a coverage layer, a constraint solver, and an architectural state model.
• The test specification layer uses a declarative language derived from the yacc(1) input language to define valid test spaces and enumerate coverage points in that space. The coverage layer generates specific testcases for each type of coverage supported by the test generation system. For example, the coverage layer can produce a back-to-back sequence of loads and stores to cover address hazards. The detailed chore of getting the registers in the processor to the required address and store data is left to the two lower layers. The constraint solver accepts requests from the coverage layer to move a pool of registers to a specific set of states. The constraint solver attempts to build a short sequence of assembly instructions that convert the current state into the requested state while using instructions that propagate the current state, such that the observability of defects in prior operations is maintained. The processor and memory system state are managed by the lowest layer: the architectural state model. The architectural state model includes the CPU register state, a sparse memory model and functions emulating the instruction set that modify these state elements.
• The paper includes examples from the CPP packet processing engine of test specifications, coverage event definitions and assembly code solutions from the constraint solver.
• Don graduated from Rose-Hulman Institute of Technology in 1984 with a BSEE and from the University of South Florida in 1988 with a MSEE. He worked at Texas Instruments from 1984 to 2001 and led projects including Sun, HP and DEC floating point and vector processors, x86 CPU development and VLIW DSP architecture. Don joined Navarro Networks in 2001 which was acquired by Cisco Systems in 2002. At Cisco, Don is a principal engineer and responsible for packet processor architecture and part of next generation router architecture committee. Don has published several peer reviewed journal papers and 23 US patents.

Greg Tierney - Avid Technology

Design Verification Using SystemC - pdf

• Boston - Q1 2007
• Experiences with SystemC at Avid:
  This talk will discuss why Avid chose the SystemC class library for writing verification code, and what is good and bad about the experience. Avid runs a mixed language simulation environment with most design RTL described in VHDL and most verification code written in C++. Topics include: navigating the language crossing boundary, creating connection interfaces between modules and binding them, using constrained randomization and other features from SystemC's verification library (SCV), defining Transaction Level Model (TLM) interfaces at more abstract layers in the test bench, and organizing behavioral code into thread and method processes. There will be some examples, revelations, and pitfalls in the SystemC approach. Mostly, this talk will give one engineer's opinion on how SystemC is suited for verification use
• Greg Tierney is presently a principal hardware engineer at Avid Technology. He has over 10 years of industry experience at ASIC and FPGA design verification and computer architecture. Greg has been writing C++ to model hardware throughout his career to verify 15 completed chips and to invent and file 36 patents in computer architecture (10 issued). Greg has a BSEE from Tufts University and a Masters in Computer Engineering from the University of Massachusetts Lowell.

Joseph Zhang - Cisco Systems

Cisco Base Environment Overview - pdf

• RTP - Q3 2007
• Joseph H. Zhang obtained his Master's degree in Computer Engineering from the University of Waterloo, in Canada. He currently work as a verification lead for Cisco Systems. Joseph has over 7 years of experience leading verification projects for complex multi-million gate ASICs using Specman/e. He is one of the principal architects for his business unit's base verification environment which achieved over 95% unit-level to chip-level testbench reuse on their most recent SOC. Prior to joining Cisco, Joseph worked at several start-up companies focusing on both RTL design and verification.