Events

General Verification

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Grant Martin - Chief Scientist, Tensilica, Inc., Santa Clara, California

Grant Martin is a Chief Scientist at Tensilica, Inc. in Santa Clara, California. Before that, Grant worked for Burroughs in Scotland for six years; Nortel/BNR in Canada for 10 years;  and Cadence Design Systems for nine years, eventually becoming a Cadence Fellow in their Labs.   He received his Bachelor's and Master's degrees in Mathematics (Combinatorics and Optimisation) from the University of Waterloo, Canada, in 1977 and 1978.

Grant is a co-author or co-editor of nine books dealing with SoC design, SystemC, UML, modelling, EDA for integrated circuits and system-level design, including the first book on SoC design published in Russian.    His most recent book, ESL Design and Verification, written with Brian Bailey and Andrew Piziali, was published by Elsevier Morgan Kaufmann in February, 2007.

He was co-chair of the DAC Technical Programme Committee for Methods for 2005 and 2006. His particular areas of interest include system-level design, IP-based design of system-on-chip, platform-based design, and embedded software.    Grant is a Senior Member of the IEEE.

Sadik Ezer - Lead Verification Engineer, Diamond Video Products, Tensilica Inc.

Sadik Ezer is the Lead Verification Engineer of Diamond Video products at Tensilica Inc. He has been with Tensilica for six years. Before that he worked in SGI (Silicon Graphics Inc.), Mountain View for four years as Senior Verification Engineer, and in Managed Information Technology Systems (MITS) in Sydney, Australia, as Software Engineer for two years. He received his Bachelor's and Master's degrees (on DSP and Image Processing)  in E.E. from Bogazici University, Istanbul, Turkey, in 1990 and 1992. He has three conference papers, the last one was presented at DAC 2005, titled Smart Diagnostics for Configurable Processor Verification.

For the first part of the talk, Grant will give an overview of Tensilica's ESL models and tools strategy, and will draw on examples based on system level design of and with our video product, as well as other capabilities we have developed for system level design and verification.

For the second part, Sadik will focus mainly on the Dual Core Diamond Video System verification. He will talk about the system-level testing of a hardware design tailored to run video applications, reuse of transactor-based verification components, HW/SW co-verification using emulation, synchronous debugging of multi core systems, and power analysis challenges of video applications.