Events

General Verification

Jason Stinson - Principal Engineer, Enterprise Microprocessor Group, Intel

Pre-Si Verification for Post-Si Validation - pdf

Jason is a principal engineer in the Enterprise Processor Division at Intel Corporation. He received his B.S. and M.S. degrees in electrical engineering from Stanford University in 1990 and 1991, respectively. In 1992, he joined Intel Corporation in the Microprocessor Design Division, working on the design of the original Pentium® Processor. For the past twelve years, Jason has been part of various microprocessor design projects at Intel, including the Pentium II Processor, Mobile Pentium II Processor and Celeron® Processor. During this timeframe, he has split his time between design methodology and post-silicon validation. In the area of design and design methodology, Jason has been responsible for dynamic circuits, clocking, signal integrity and timing analysis on various projects. In the area of post-silicon validation, Jason’s expertise areas are primarily in marginality validation and frequency debug.

For the past four years, Jason has been the circuit technical lead for the 0.13um Itanium® 2 Processor, responsible for both the global design methodologies as well as post-silicon validation.

Jason has authored 10 papers in refereed conference and technical journals. He has been awarded 3 US patents. Additionally, Jason has taught classes in advanced digital design at Stanford University and post-silicon validation at international conferences.

Paul Zehr - Principal Engineer, Intel

Intex Xeon Pre-Silicon Validation - pdf

Paul is currently a Xeon processor pre-silicon validation technical lead. Previously, he led various pre-silicon and post-silicon functional validation efforts on many IPF projects, including the first IPF processor, Merced. Paul developed pre-silicon cluster test environments, including the first cache-MP cluster environment capable of using either real chipset RTL, or an emulated chipset model. As a technical leader, he was responsible for the micro-architectural full chip checker. In post silicon, he has developed several test generators focusing on both functional verification as well as circuit marginality testing. The post silicon MP test generation tool developed for IPF processors has been ported for use on ia32 processors in order to stress certain aspects of the design. Paul initiated and led test content generation forums, focusing on improving post silicon test coverage utilizing a wide variety of test generation techniques for functional correctness.

Paul joined Intel in January of 1996, has one patent, and has authored 5 papers. Before joining Intel, Paul spent nine years in the IBM mainframe division as a design and validation engineer. His accomplishments there include team leadership of TBS switch chip validation and mainframe cache validation. He was responsible for the design of four bipolar chips in the ES9000 cache, and designed the 121-chip cache TCM (Thermo-Cooled Module) on the ES9000.

In his spare time, Paul enjoys SCUBA diving, little league, and spending time with his family.