Validation and Design in a Small Team Environment

William R. Flederbach, Qualcomm CDMA Technologies - Processor Solutions

Matthew D. Clark, Ph.D, Northrop-Grumman IT (TASC), Raleigh, NC.

Validation and Design in a Small Team Environment

Performing IC validation can be very complex and very expensive in terms of both resources (skills and tools) and in terms of schedules and cost.  As an example, one metric says that for every designer involved in the project, there should be 2.5 verification staff. If your project team is only four people, and your only tool is a set of ModelSim licenses, what steps have to be taken to produce a quality product in short design cycle? This talk will describe how a software group at Northrop Grumman constrained the design and verification environment to allow a small team to produce designs in a rapid response environment.

Matthew Clark is a Communications Systems Engineer at Northrop Grumman - Information Systems, and has previously been employed as an ASIC/FPGA designer and team lead at Intel, Nortel, and Raytheon. His research interests cover all areas of implementing analog and digital signal processing functions in digital hardware. Matthew earned a Ph.D in ECE, an MSEE, and B.Computer Engineering from the Georgia Institute of Technology, as well as a B.S. from St. Andrews Presbyterian College

DVClub membership is free and is open to all non-service provider semiconductor professionals. Most members work in verification, but there are also plenty of entrepreneurs, professors, students, managers, investors, and even design engineers who attend. Participation by service providers (solicitors) is limited to event sponsors, who supply the funds for DVClub events.

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