Design Verification Club

General Verification

     

Don Steiss - Cisco

Don graduated from Rose-Hulman Institute of Technology in 1984 with a BSEE and from the University of South Florida in 1988 with a MSEE. He worked at Texas Instruments from 1984 to 2001 and led projects including Sun, HP and DEC floating point and vector processors, x86 CPU development and VLIW DSP architecture. Don joined Navarro Networks in 2001 which was acquired by Cisco Systems in 2002. At Cisco, Don is a principal engineer and responsible for packet processor architecture and part of next generation router architecture committee. Don has published several peer reviewed journal papers and 23 US patents.

Abstract:

Design verification on embedded processors is a difficult problem that has traditionally relied on a small number of high-quality hand-generated tests augmented by a large number of directed random tests. The directed random tests are usually of lower coverage quality than the hand-generated tests.

This paper describes a layered self-checking test generation approach that allows for manual or automatic specification of coverage events on top of software layers that transform the processor state to the desired state for the next coverage event without manual code generation. The resulting tests have known coverage with the productivity of directed random tests.

The test generator is built in four layers: a test specification layer, a coverage layer, a constraint solver, and an architectural state model.

The test specification layer uses a declarative language derived from the yacc(1) input language to define valid test spaces and enumerate coverage points in that space. The coverage layer generates specific testcases for each type of coverage supported by the test generation system. For example, the coverage layer can produce a back-to-back sequence of loads and stores to cover address hazards. The detailed chore of getting the registers in the processor to the required address and store data is left to the two lower layers. The constraint solver accepts requests from the coverage layer to move a pool of registers to a specific set of states. The constraint solver attempts to build a short sequence of assembly instructions that convert the current state into the requested state while using instructions that propagate the current state, such that the observability of defects in prior operations is maintained. The processor and memory system state are managed by the lowest layer: the architectural state model. The architectural state model includes the CPU register state, a sparse memory model and functions emulating the instruction set that modify these state elements.

The paper includes examples from the CPP packet processing engine of test specifications, coverage event definitions and assembly code solutions from the constraint solver.