Design Verification Club

11.30

Networking, drinks and buffet

12.00

“Verilator; fast, free, but for me?” - pdf

Wilson Snyder – developer of “Verilator”

Join this presentation on the role, advantages and downsides of open source simulation the DV environment, and the presenter's learnings from choosing, leveraging and contributing to DV open source in general. Specific tips on getting started and using Verilator will benefit those ready to use it in their own environments.

Wilson Snyder is a consulting engineer with Cavium Networks in Marlboro, Massachusetts, USA. A graduate of Rensselaer, he has worked at Digital Semiconductor and SiCortex, performing ASIC design and microprocessor architecture, and Maker Communications, and Sun Microsystems, where he designed network processing chips. He makes regular and numerous contributions to public domain engineering tools, such as Verilog-Mode for Emacs and Verilator, available off his Veripool.com web site.

12.40

“Architecture For Massively Parallel HDL Simulations” - pdf

Rich Porter, Art of Silicon

Designs are ever more complex and require more cycles of simulation, but servers have more cores and compute power. This makes fast, license free and scalable simulation a very attractive method for accelerating verification. Event driven simulators remain the gold standard for sign off, so how can we utilize this unrestricted simulation resource to reduce design times without getting any nasty surprises at the end of the project? We present some aspects of the flow developed at Art of Silicon, which maximises the use of common infrastructure allowing verilator and event driven simulators to be run together seamlessly. Verilator can be used when elapsed real time is critical, and event driven simulation is used in full regression and sign off.

Rich Porter is Technical Director of Art of Silicon, a silicon IP and consultancy company which he co-founded in 2005. Rich has been in the industry for 15 years and previously worked at Element-14 and STMicroelectronics. Rich spent the early part of his career creating maintainable and reusable RTL, subsequently he has been involved in verification. His interests include bringing these two disciplines together by specifying design features that aid the verification process.

12.55

“Free Electronic Lab: Hardware engineering made easy” - pdf

Chitlesh Goorah, Digital Design Engineer, ON Semiconductor

Free Electronic Lab (formerly Fedora Electronic Lab) is dedicated to support the innovation and development brought by open source Electronic Design Automation (EDA) community. As an EDA provider, FEL maps in three methodologies {design, simulation and verification} with open source EDA software to give a better hardware design experience.

The presentation will demonstrate how the engineers can benefit from enterprise-class open source solutions and how the FEL development team plays a vital role to solve different difficulties hardware designers encountered with open source EDA software in the past, and how FEL is now helping them.

Chitlesh Goorah is the Free Electronic Lab founder. He works at ON Semiconductor as a Digital Design Engineer and holds a master degree in Micro-Nano Electronics engineering. In his leisure time, he strives to keep the FEL in pace as an advance electronic design and simulation platform. Interoperability is one of his main targets for the success of the EDA community and works hand-in-hand with many upstream EDA developers.

13.25

“Processor verification using open source tools and the GCC regression test suite: A case study” - pdf

Dr Jeremy Bennett, founder and CEO of Embecosm

A key part of processor verification is ensuring that the instruction set will correctly handle all the code it may ever be asked to run. The GNU Compiler Collection (GCC) tools include over 40,000 tests of the C compiler alone. These provide an excellent test set of a processor's instruction set.

We report a case study using the OpenRISC 1000, in which this test set was used to verify both the architectural reference model and the design itself. The design model in SystemC is built directly from the RTL using Verilator.

We conclude by showing how this leads to a completely general approach to exercising designs using SystemC models, including a recent example from KTH Stockholm, also using the OpenRISC 1000.

Embecosm was founded by Dr Jeremy Bennett, an expert on hardware modeling and embedded software development. Prior to founding Embecosm, Dr Bennett was Vice President of ARC International plc, following their acquisition of Tenison Design, developers of the VTOC tool set for cycle accurate modeling of SoC hardware, where he had been CEO and CTO.

Before moving into industry in the mid-1990's, Dr Bennett pursued academic research into computer architecture, modeling and compiler technology at Cambridge and Bath Universities in the UK. He is author of numerous academic papers as well as the popular textbook "Introduction to Compiling Techniques" (McGraw-Hill 1990, 1995, 2003).

Dr Bennett holds an MA and PhD in Computer Science from Cambridge University. He is a Member of the British Computer Society, a Chartered Engineer and a Chartered Information Technology Professional.

13.50

Networking, drinks and buffet

14.00

Finish