Events

General Verification

Mark A Firstenberg, IBM

Experience with Formal Methods, Especially Sequential Equivalence Checking - pdf

The relationship between formal and simulation based verification methods, as well as when and where they are applicable, will be discussed.  Semi-formal methods, boolean equivalence checking and sequential equivalence checking will be defined.  The application of sequential equivalence checking on two projects will be detailed, including lessons learned.

Mark Firstenberg joined IBM's Systems and Technology Group in July 2004 as a Senior Technical Staff Member.  He has been developing and deploying a flow which systematically uses sequential equivalence checking across an entire project.  Previously, Mark served as the RTL methodologist for Sun's UltraSPARC V processor, supported design verification tools and flows at Stratus Computer and investigated hardware/software co-design at Viewlogic Systems.  At Digital Equipment Corporation, Mark wrote two cycle-based simulators, served as a logic designer for the VAX 9000 (receiving four patents) and wrote microcode for the VAX 8800.  Mark holds a BSEE from Cornell University.

Greg Tierney, Avid Technology

Design Verification Using SystemC - pdf

Experiences with SystemC at Avid:
This talk will discuss why Avid chose the SystemC class library for writing verification code, and what is good and bad about the experience. Avid runs a mixed language simulation environment with most design RTL described in VHDL and most verification code written in C++. Topics include: navigating the language crossing boundary, creating connection interfaces between modules and binding them, using constrained randomization and other features from SystemC's verification library (SCV), defining Transaction Level Model (TLM) interfaces at more abstract layers in the test bench, and organizing behavioral code into thread and method processes. There will be some examples, revelations, and pitfalls in the SystemC approach. Mostly, this talk will give one engineer's opinion on how SystemC is suited for verification use

Greg Tierney is presently a principal hardware engineer at Avid Technology. He has over 10 years of industry experience at ASIC and FPGA design verification and computer architecture. Greg has been writing C++ to model hardware throughout his career to verify 15 completed chips and to invent and file 36 patents in computer architecture (10 issued). Greg has a BSEE from Tufts University and a Masters in Computer Engineering from the University of Massachusetts Lowell.