Design Verification Club
Event
- Title:
- Austin - Topics in Verification Metrics
- When:
- 12.15.2010 11.00 h - 17.00 h
- Where:
- Cool River Cafe - Austin, TX
- Category:
- Austin
Description
Presentations:
Using Bug Arrival Rates to Predict the Future - PDF Slides - Sample Metrics
Greg Smith -- Sr. Verification Manager at Oracle
Abstract:
So much of today's metrics used to gauge the progress of a verification project are backwards looking - telling us what ground we have covered. In addition, many metrics commonly in use are subjective and prone to human errors of omission. I would like to present a different approach to DV project metrics using bug arrivals to actually provide some predictive capability as well as aid in overall project planning.
Bio:
· Greg Smith has over 25 years of experience in the design of processors, ASICs and full systems.
· Greg Smith is currently a Senior Manager of Design Verification for SPARC cores at Oracle - a position he has held for 5 years.
· Prior to Oracle, Greg managed the design and verification of fault tolerant ASIC designs for Tandem Computers. It was at Tandem/HP that Greg developed a passion for metrics as a tool for determining design quality and completion which lead to the tape out of a dozen ASICs each of which had first pass success.
· Prior to Tandem Greg was managing the development of a VLIW mini-supercomputer system at a
company called MultiFlow in New Haven, Connecticut.
· Greg started his career designing minicomputer systems at Prime Computer in Natick, Mass.
· Greg holds a BSCS from Ohio Sate and bleeds scarlet and gray.
High Performance Collection of Coverage Metrics Using a Relational Database Backend - PDF Slides
James Roberts -- Sr. Verification Engineer at Oracle
Abstract:
A database is an ideal medium for collecting and analyzing coverage. At Oracle, we marry our Oracle database with coverage collection of our verification, and then use SQL to extract coverage metrics on-demand. This presentation outlines an intuitive scheme for database collection of coverage, and presents data showing the scalability and the high bandwidth this scheme is able to handle.
Bio:
· James Roberts is a Senior Verification Engineer in UltraSparc design at Oracle (formerly Sun).
· Prior to Sun, he worked at Intel as a Circuit Design Engineer and Verification Engineer.
· He also worked on physical verification and custom design at a couple other companies, including Freescale in Austin.
· Mr. Roberts holds an MSEE from Georgia Tech, and is a card-carrying Yellowjacket.
Stick a Fork in it: Applications for SytstemVerilog Dynamic Processes - PDF Slides (requires registration)
Doug Smith -- Doulos
Agenda
| 11.00 | Doors Open |
| 11.00-12.00 | Registration and Networking |
| 12.00-13.00 | Lunch Served Presentations by Greg Smith and James Roberts of Oracle |
| 13.00-13.30 | Q&A with Presenters & Networking - Coffee and Refreshments Served |
| 13.30-14.15 | Verification Tutorial I with Doug Smith of Doulos Title: "Stick a fork in it: Applications for SystemVerilog Dynamic Processes Focus: Verification and modeling Audience: Verification engineers, but designers may find interesting Skill level: Basic to Advanced Verilog/SystemVerilog Description: In Verilog, processes come in the static form of always and initial blocks, concurrent assignments, and the fork..join statement. SystemVerilog introduces dynamic processes in the form of new fork..join statements and the std::process class. This presentation explores several applications for dynamic processes in verification and behavioral modeling such as how verification methodologies create independently executing components and control simulation phasing, isolating random number generators for test reproducibility, parallelizing testbench interaction with DPI code, and a way of using dynamic processes with SystemVerilog interfaces to create bus resolution functions and model analog behavior. |
| 14.15-14.30 | Break / Q & A |
| 14.30-15.00 | Verification Tutorial II with Doug Smith of Doulos Title: Getting Started with OVM (UVM) Focus: Verification Audience: Designers and verification engineers adopting or considering OVM (UVM) Skill Level: Intermediate - recommended knowledge of class-based SystemVerilog Description: Basic introduction to OVM. Simple environment presented showing the steps and code required to create an OVM (UVM) testbench environment. |
| 15.00-15.15 | Break / Q & A |
| 15.15-15.45 | Verification Tutorial III with Doug Smith of Doulos Title: Introduction to SystemVerilog Assertions (SVA) Focus: Verification Audience: Design and verification engineers Skill Level: Basic - no SystemVerilog required, but some an HDL recommended Description: Basic introduction to the SystemVerilog assertion language. Intended for those who have no knowledge of SVA and interested in what it's all about. |
| 15.45-16.00 | Closing Q & A |
Venue
- Venue:
- Cool River Cafe - Website
- Street:
- 4001 Parmer Lane
- ZIP:
- 78727
- City:
- Austin, TX
- Country:
-
