Design Verification Club

Speaker:
John M. Ludden - IBM Systems and Technology Group

Abstract:
IBM's POWER7 processor chip officially began shipping in IBM's POWER Systems servers in early 2010. The Power 750 Server is the industry's highest performing 4-socket system. The POWER7 chip contains 8 processor cores, each capable of executing up to 4 threads simultaneously. This presentation will give an overview of the verification methodology for the POWER7 processor core mainline function. This methodology led to outstanding first-pass hardware quality. There will be a brief introduction to the POWER7 chip and core microarchitecture followed by detailed discussions of Simultaneous Multi-Threading (SMT) verification, test plan development, coverage methodology and a look at IBM's simulation acceleration platform usage.

Bio:
John Ludden is a senior technical staff member at IBM where he has over 18 years of experience in design verification spanning mainframes, x86 and PowerPC processor based systems. He has been the architecture verification lead engineer for IBM's POWER3/4/5/6 processors and is a member of IBM's Verification Advisory Team. For the past 14 years, John has worked with IBM's test generation research team in Haifa, Israel to improve instruction-level test generation capabilities in order to address out-of-order execution, symmetric multi-processing and simultaneous multi-threading (SMT) processor verification requirements. John received a Corporate Award from IBM for his leadership in defining and executing the POWER5 SMT verification plan. He has co-authored three papers and currently holds two patents in microprocessor verification. John received his BSEE from the Rochester Institute of Technology in Rochester, New York in 1990.

Presentation Notes:
PDF Slides