Please join us for the next DVClub Silicon Valley event! You will be treated to a complimentary catered lunch while you network with industry collegues, and enjoy an enlightening presentation.

Greg Smith of Oracle Corporation will be our speaker, and Andy Stein of Avery Design Systems will present the tutorial.

We look forward to seeing you there!

Wednesday, October 11, 2017 from 11:30 AM to 1:50 PM

Dave and Buster's
940 Great Mall Drive
Milpitas, CA 95035
View Map


11:30am Doors Open / Networking

Lunch and Presentation by Greg Smith, Oracle
"Functional Coverage is Useless!"

1:00pm Tutorial by Andy Stein, Avery Design Systems
"Improving 'Gate Simulation Signoff' throughput by handling the noise from False X's"

Registration Now Open - Click to RSVP

Greg Smith

Oracle Corporation

“Functional Coverage is Useless!”

Greg's talk today will observe the evolution in the use of coverage to measure verification completeness and tape out readiness. His talk suggests that we are at an inflection point in the evolution of coverage where current methods are grossly inadequate. He will suggest some directions in which coverage may evolve to meet the demands of today's complex SOCs.


Greg Smith has been a verification engineer for all of his 30 year career. Processor verification has been the primary focus for nearly all of that time. Greg is a Director of Processor verification at Oracle/Sun where he has worked for the past 10+ years. Before that Greg worked at HP and Multiflow. Greg's role at Oracle, besides managing the verification of next generation SPARC cores, is as a driver of innovation to devise new techniques to improve tape out quality and improve engineering efficiency. Greg is a passionate proponent of the use of metrics to measure verif efficiency and quality.



Andy Stein

Avery Design Systems

"Improving 'Gate Simulation Signoff' throughput by handling the noise from False X's"

Many companies that are using gate simulation to verify functionality already understand that despite efforts to clean up potential “X” issues in RTL, their post-synthesis and optimization results can produce additional sources of “X” in their gate netlist. Some of the effects of the “X's” in gate simulation are not real, but are mainly artifacts of Verilog simulation being overly pessimistic. As design and verification engineers race against the clock to analyze the results to find real problems, the noise created by the false X’s can cause too much time wasted. As such, some companies have more brute force methods, such as initializing all flops to some arbitrary value and run multiple simulations to hope they have not masked a real issue. Avery Design Systems has had a product on the market for many years, SimXACT, to help companies take a more conservative approach to removing the noise from false X’s, by applying the tool dynamically during simulation to remove those false X’s and using formal analysis to prove the correctness of the fixes.