The summer is heating up, and so is DVClub Austin in anticipation of our June event. This month we are featuring two local Austin speakers. First up, just as you thought you were establishing some nice job security, Greg Smith from Oracle is going to explain why "Functional Coverage is Useless!" ... yikes! After Greg makes his case, fresh off of a 1st place win at DVCon this year we'll listen to Stan Sokorac's prize-winning presentation "Optimizing Random Test Constraints Using Machine Learning Algorithms." All the cool kids are doing machine learning these days, this should be good.

As always, this is a free catered lunch with plenty of opportunity to catch up with old friends and colleagues, meet new friends, and network with others in the industry. Special thanks once again to our DVClub Sponsors for making this event possible..

Norris Conference Center
2525 W Anderson Ln #365
Austin, TX 78757
Wednesday, June 28, 2017 from 11:30 AM to 1:30 PM (CST)
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We look forward to seeing you there!

Agenda

11:30am Doors Open / Networking
12:00pm

Lunch and Presentations

  • Greg Smith - “Functional Coverage is Useless!”
  • Stan Sokorac - “Optimizing Random Test Constraints Using Machine Learning Algorithms”
1:00pm-1:30pm Networking

Registration Now Open - Click to RSVP

Greg Smith

Oracle Corporation

“Functional Coverage is Useless!”

Greg's talk today will observe the evolution in the use of coverage to measure verification completeness and tape out readiness. His talk suggests that we are at an inflection point in the evolution of coverage where current methods are grossly inadequate. He will suggest some directions in which coverage may evolve to meet the demands of today's complex SOCs.

Bio:

Greg Smith has been a verification engineer for all of his 30 year career. Processor verification has been the primary focus for nearly all of that time. Greg is a Director of Processor verification at Oracle/Sun where he has worked for the past 10+ years. Before that Greg worked at HP and Multiflow. Greg's role at Oracle, besides managing the verification of next generation SPARC cores, is as a driver of innovation to devise new techniques to improve tape out quality and improve engineering efficiency. Greg is a passionate proponent of the use of metrics to measure verif efficiency and quality.


Stan Sokorac

ARM

“Optimizing Random Test Constraints Using Machine Learning Algorithms”

A staple of modern verification is constrained random simulation, which involves generation of random transaction streams controlled through a set of adjustable constraints. One of the major challenges of verification is finding the right combinations of constraints to produce the most stressful tests with the widest variety of random stimulus. With typical nightly and weekly regressions generating billions of simulation cycles in tens of thousands of tests, it is impossible for a human to process all available data. Verification engineers therefore use various aggregation and approximation methodologies, such as code and functional coverage, to gain insight into regression results. However, the fields of machine learning and data mining excel at exactly these kinds of problems by finding patterns in this vast repository of data and extrapolating insights to guide us in the best direction. This presentation describes a methodology in which coverage results and machine learning algorithms are used to generate tests most likely to find new bugs in a design.

Bio:

Stan Sokorac is a Computer Engineering graduate from University of Toronto, and has worked at IBM, ATI, AMD, and ARM, in various roles including software development, ASIC design, verification, and management. He is currently a Sr. Principal Design Engineer at ARM, driving verification of the cache coherent memory subsystem on the next-generation ARM® Cortex-A® CPU core. He is passionate about introducing new methodologies and developing new flows that improve verification efficiency and effectiveness.

 

 

 

 

 

 

 

"Systemverilog Interface Classes: More Useful Than You Thought"

Stan Sokorac - About the Presenter:

Stan Sokorac is a Computer Engineering graduate from University of Toronto, and has worked at IBM, ATI, AMD, and ARM, in various roles including software development, ASIC design, verification, and management. He is currently a Sr. Principal Design Engineer at ARM, driving verification of the cache coherent memory subsystem on the next-generation ARM® Cortex-A® CPU core. He is passionate about introducing new methodologies and developing new flows that improve verification efficiency and effectiveness.

About the Presentation:

Interface classes were introduced in SystemVerilog 2012, but have seen little adoption in the verification community. While this construct is well established in the software development world, most verification engineers either don’t know about it or don’t see any benefit in using it. The goal of this presentation is to demonstrate the value of interface classes by sharing some of the most important uses which were employed during the verification of the next-generation ARM® Cortex-A® CPU core.

 

"Functional Coverage Collection for Analog Circuits"

Zhipeng Ye - About the Presenter:

Zhipeng Ye is a verification lead in Texas Instruments in Dallas TX. Before joining TI, he worked for Maxim Integrated in Chandler Arizona and Australia Semiconductor Technology Company in Adelaide Australia. He holds a Ph.D. degree from University College Cork, Ireland.

About the Presentation:

Abstract-In this presentation, Analog Coverage Collector (ACC) is proposed to serve as a tool that analog designers can utilize to pass the analog design information, even when this information is deep inside the schematic hierarchy, to verification engineers who would handle chip level AMS/functional testbench for mixed signal designs. Based on that information, verification engineers are able to construct meaningful covergroups at the top level testbench in order to measure the chip-level functional coverage as accurately as possible. We show that analog designers can easily use ACC, and an example is presented to demonstrate the flow to collect analog coverage.