On December 23, 2009 the Accellera Verification IP Technical Subcommittee (VIP TSC) voted to make OVM the base of the new UVM and to deliver UVM 1.0 in Q1. This is great news for OVM users and the verification community in general.

For those not using OVM yet, this news clearly indicates that it’s time to move to OVM because the VIP TSC is committed to backward compatibility with OVM. For those using VMM, it is the right time to start the migration process.

Cadence can help with both OVM Startup and VMM Migration services leveraging the interoperability library built by the VIP TSC. While the VIP TSC will consider technology from sources like OVM, VMM, and other contributions, the bottom line is that Accellera voted overwhelmingly to make UVM = OVM and that is great news for verification engineers – one unified methodology has arrived and it is OVM.

By Doug Smith of Doulos

Conferences aren’t my favorite events to attend. They tend to be dominated by the big three EDA companies, and the messages are usually just a variation on what was said last year. However, there is always something useful to glean if you listen hard enough, and I think DVCon this year is no exception.

While DVCon is generally more of a verification conference, I found design related topics surprisingly absent. Cliff Cummings presented a good paper on using SystemVerilog’s unique, priority, and 1800-2009’s unique0 constructs, but other than that, everything centered on verification except for some brief discussion on C synthesis at a panel and the SystemC synthesizable subset at the OSCI tutorial session. Verification continues to dominate the industry’s focus as well as high-level modeling.

Read More >>